From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rodrigo Vivi Subject: Re: [PATCH] drm/i915/psr: Chase psr.enabled only under the psr.lock Date: Fri, 6 Apr 2018 15:18:16 -0700 Message-ID: <20180406221816.GG8964@intel.com> References: <20180405114915.29609-1-chris@chris-wilson.co.uk> <7e7b4336aefd6e6cf993150c1a83d214c161a210.camel@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTPS id E30316EAE1 for ; Fri, 6 Apr 2018 22:18:17 +0000 (UTC) Content-Disposition: inline In-Reply-To: <7e7b4336aefd6e6cf993150c1a83d214c161a210.camel@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: "Souza, Jose" Cc: "intel-gfx@lists.freedesktop.org" , "R, Durgadoss" , "stable@vger.kernel.org" List-Id: intel-gfx@lists.freedesktop.org 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LWdmeCBtYWlsaW5nIGxpc3QKSW50ZWwtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczov L2xpc3RzLmZyZWVkZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2ludGVsLWdmeAo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga17.intel.com ([192.55.52.151]:64774 "EHLO mga17.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751807AbeDFWSR (ORCPT ); Fri, 6 Apr 2018 18:18:17 -0400 Date: Fri, 6 Apr 2018 15:18:16 -0700 From: Rodrigo Vivi To: "Souza, Jose" Cc: "intel-gfx@lists.freedesktop.org" , "chris@chris-wilson.co.uk" , "R, Durgadoss" , "stable@vger.kernel.org" Subject: Re: [Intel-gfx] [PATCH] drm/i915/psr: Chase psr.enabled only under the psr.lock Message-ID: <20180406221816.GG8964@intel.com> References: <20180405114915.29609-1-chris@chris-wilson.co.uk> <7e7b4336aefd6e6cf993150c1a83d214c161a210.camel@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <7e7b4336aefd6e6cf993150c1a83d214c161a210.camel@intel.com> Sender: stable-owner@vger.kernel.org List-ID: On Fri, Apr 06, 2018 at 11:12:27AM -0700, Souza, Jose wrote: > On Thu, 2018-04-05 at 12:49 +0100, Chris Wilson wrote: > > Inside the psr work function, we want to wait for PSR to idle first > > and > > wish to do so without blocking the normal modeset path, so we do so > > without holding the PSR lock. However, we first have to find which > > pipe > > PSR was enabled on, which requires chasing into the PSR struct and > > requires locking to prevent intel_psr_disable() from concurrently > > setting our pointer to NULL. > > > > Fixes: 995d30477496 ("drm/i915: VLV/CHV PSR Software timer mode") > > Signed-off-by: Chris Wilson > > Cc: Durgadoss R > > Cc: Rodrigo Vivi > > Cc: # v4.0+ > > Feel free to add: > Reviewed-by: Jose Roberto de Souza > > > --- > > drivers/gpu/drm/i915/intel_psr.c | 82 +++++++++++++++++++++--------- > > ---------- > > 1 file changed, 44 insertions(+), 38 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_psr.c > > b/drivers/gpu/drm/i915/intel_psr.c > > index 2d53f7398a6d..69a5b276f4d8 100644 > > --- a/drivers/gpu/drm/i915/intel_psr.c > > +++ b/drivers/gpu/drm/i915/intel_psr.c > > @@ -775,53 +775,59 @@ void intel_psr_disable(struct intel_dp > > *intel_dp, > > cancel_delayed_work_sync(&dev_priv->psr.work); > > } > > > > -static void intel_psr_work(struct work_struct *work) > > +static bool psr_wait_for_idle(struct drm_i915_private *dev_priv) > > { > > - struct drm_i915_private *dev_priv = > > - container_of(work, typeof(*dev_priv), > > psr.work.work); > > - struct intel_dp *intel_dp = dev_priv->psr.enabled; > > - struct drm_crtc *crtc = dp_to_dig_port(intel_dp)- > > >base.base.crtc; > > - enum pipe pipe = to_intel_crtc(crtc)->pipe; > > + struct intel_dp *intel_dp; > > nitpick: Why not already set it? > struct intel_dp *intel_dp = dev_priv->psr.enabled; > > > > + i915_reg_t reg; > > + u32 mask; > > + int err; > > + > > + intel_dp = dev_priv->psr.enabled; > > + if (!intel_dp) > > + return false; > > > > - /* We have to make sure PSR is ready for re-enable > > - * otherwise it keeps disabled until next full > > enable/disable cycle. > > - * PSR might take some time to get fully disabled > > - * and be ready for re-enable. > > - */ > > if (HAS_DDI(dev_priv)) { > > > nitpick: While on that you could replace this for: > > if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) { > > > if (dev_priv->psr.psr2_enabled) { > > - if (intel_wait_for_register(dev_priv, > > - EDP_PSR2_STATUS, > > - EDP_PSR2_STATUS_ > > STATE_MASK, > > - 0, > > - 50)) { > > - DRM_ERROR("Timed out waiting for > > PSR2 Idle for re-enable\n"); > > - return; > > - } > > + reg = EDP_PSR2_STATUS; > > + mask = EDP_PSR2_STATUS_STATE_MASK; > > } else { > > - if (intel_wait_for_register(dev_priv, > > - EDP_PSR_STATUS, > > - EDP_PSR_STATUS_S > > TATE_MASK, > > - 0, > > - 50)) { > > - DRM_ERROR("Timed out waiting for PSR > > Idle for re-enable\n"); > > - return; > > - } > > + reg = EDP_PSR_STATUS; > > + mask = EDP_PSR_STATUS_STATE_MASK; > > } > > } else { > > - if (intel_wait_for_register(dev_priv, > > - VLV_PSRSTAT(pipe), > > - VLV_EDP_PSR_IN_TRANS, > > - 0, > > - 1)) { > > - DRM_ERROR("Timed out waiting for PSR Idle > > for re-enable\n"); > > - return; > > - } > > + struct drm_crtc *crtc = > > + dp_to_dig_port(intel_dp)->base.base.crtc; I'm afraid that the issue is this pointer here. So this will only mask the issue. Should we maybe stash the pipe? :/ > > + enum pipe pipe = to_intel_crtc(crtc)->pipe; > > + > > + reg = VLV_PSRSTAT(pipe); > > + mask = VLV_EDP_PSR_IN_TRANS; > > } > > + > > + mutex_unlock(&dev_priv->psr.lock); > > + > > + err = intel_wait_for_register(dev_priv, reg, mask, 0, 50); > > + if (err) > > + DRM_ERROR("Timed out waiting for PSR Idle for re- > > enable\n"); > > + > > + /* After the unlocked wait, verify that PSR is still wanted! > > */ > > mutex_lock(&dev_priv->psr.lock); > > - intel_dp = dev_priv->psr.enabled; > > + return err == 0 && dev_priv->psr.enabled; > > +} > > > > - if (!intel_dp) > > +static void intel_psr_work(struct work_struct *work) > > +{ > > + struct drm_i915_private *dev_priv = > > + container_of(work, typeof(*dev_priv), > > psr.work.work); > > + > > + mutex_lock(&dev_priv->psr.lock); > > + > > + /* > > + * We have to make sure PSR is ready for re-enable > > + * otherwise it keeps disabled until next full > > enable/disable cycle. > > + * PSR might take some time to get fully disabled > > + * and be ready for re-enable. > > + */ > > + if (!psr_wait_for_idle(dev_priv)) > > goto unlock; > > > > /* > > @@ -832,7 +838,7 @@ static void intel_psr_work(struct work_struct > > *work) > > if (dev_priv->psr.busy_frontbuffer_bits) > > goto unlock; > > > > - intel_psr_activate(intel_dp); > > + intel_psr_activate(dev_priv->psr.enabled); > > unlock: > > mutex_unlock(&dev_priv->psr.lock); > > }