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received-spf: None (protection.outlook.com: microsoft.com does not designate permitted sender hosts) x-microsoft-antispam-message-info: rxPKo7YplgJl9iVNt2DJCQlQsjLpb0Nt93gVZMWygjiXUXENgiBBRpI7IaijKG6J+Se1V6rdctPBPlT3LilqDiJFOkf0dfLJDswy7eFqyBgY60lrQ1ibxCOYyDYOEuaPay3hgL2zs6uenn9TlPo+toAHz60iOwGb5ZYqJ6c5oxAqMQL/Jvk5Nh85QmsQj/xzu2MLLxN3iwgFsqmvCbQHIr0RyDjofGJdp0GCKvVCNEe1lMb64Jh17x2I8VaMcohPbOIJafoBxMn2GTbkIHk/sRZNR/PPTDuG6p8rLvfUEN1O/XSayv1C9fDIDnChCv4rU78PxSGiZGa8/QB8xgitIUZ6kvnNtz8I0VmZovGfji+LwCr8mhpywhJ+s+kFijhbgUPaTlIKO7PXGOFRm/F2VvskwRaqMAYN1zTzyaSAtjc= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-OriginatorOrg: microsoft.com X-MS-Exchange-CrossTenant-Network-Message-Id: 27b9b9f3-5a75-4d03-ca34-08d59db00873 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Apr 2018 00:20:20.2070 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 72f988bf-86f1-41af-91ab-2d7cd011db47 X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR2101MB1014 Return-Path: X-Envelope-To: <"|/home/ecartis/ecartis -s linux-mips"> (uid 0) X-Orcpt: rfc822;linux-mips@linux-mips.org Original-Recipient: rfc822;linux-mips@linux-mips.org X-archive-position: 63440 X-ecartis-version: Ecartis v1.0.0 Sender: linux-mips-bounce@linux-mips.org Errors-to: linux-mips-bounce@linux-mips.org X-original-sender: Alexander.Levin@microsoft.com Precedence: bulk List-help: List-unsubscribe: List-software: Ecartis version 1.0.0 List-Id: linux-mips X-List-ID: linux-mips List-subscribe: List-owner: List-post: List-archive: X-list: linux-mips From: Maarten ter Huurne [ Upstream commit 1f7412e0e2f327fe7dc5a0c2fc36d7b319d05d47 ] According to config2, the associativity would be 5-ways, but the documentation states 4-ways, which also matches the documented L2 cache size of 256 kB. Signed-off-by: Maarten ter Huurne Reviewed-by: James Hogan Cc: Ralf Baechle Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/18488/ Signed-off-by: James Hogan Signed-off-by: Sasha Levin --- arch/mips/mm/sc-mips.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/mips/mm/sc-mips.c b/arch/mips/mm/sc-mips.c index 548acb7f8557..394673991bab 100644 --- a/arch/mips/mm/sc-mips.c +++ b/arch/mips/mm/sc-mips.c @@ -16,6 +16,7 @@ #include #include #include +#include /* * MIPS32/MIPS64 L2 cache handling @@ -220,6 +221,14 @@ static inline int __init mips_sc_probe(void) else return 0; + /* + * According to config2 it would be 5-ways, but that is contradicted + * by all documentation. + */ + if (current_cpu_type() == CPU_JZRISC && + mips_machtype == MACH_INGENIC_JZ4770) + c->scache.ways = 4; + c->scache.waysize = c->scache.sets * c->scache.linesz; c->scache.waybit = __ffs(c->scache.waysize); -- 2.15.1