Re: [PATCH] drm/i915/gen9_lp: Increase DDI PHY0 power well enabling timeout

["Ville Syrjälä" <ville.syrjala@linux.intel.com>]

On Mon, Apr 09, 2018 at 03:27:16PM +0300, Imre Deak wrote:
> On GLK sporadic timeouts occur during PHY0 enabling. Based on logs it looks
> like they happen sometime after a system suspend/resume cycle, with the
> same power well enabling succeeding both before and after the failed
> one and no other problems observed. The current timeout in the code is
> not actually specified by BSpec, so let's try to increase that until a
> BSpec update.

Looks like we've always used 1ms on CHV. I couldn't find any specific
notes on how long we should poll in any of the CHV PHY docs. So I assume
we just picked 1ms since it seemed sufficient.

Doing the same for BXT/GLK seems reasonable to me.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105771
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dpio_phy.c | 11 ++++++-----
>  1 file changed, 6 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index c8e9e44e5981..00b3ab656b06 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -380,13 +380,14 @@ static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
>  	 * all 1s.  Eventually they become accessible as they power up, then
>  	 * the reserved bit will give the default 0.  Poll on the reserved bit
>  	 * becoming 0 to find when the PHY is accessible.
> -	 * HW team confirmed that the time to reach phypowergood status is
> -	 * anywhere between 50 us and 100us.
> +	 * The flag should get set in 100us according to the HW team, but
> +	 * use 1ms due to occasional timeouts observed with that.
>  	 */
> -	if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
> -		(PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) {
> +	if (intel_wait_for_register_fw(dev_priv, BXT_PORT_CL1CM_DW0(phy),
> +				       PHY_RESERVED | PHY_POWER_GOOD,
> +				       PHY_POWER_GOOD,
> +				       1))
>  		DRM_ERROR("timeout during PHY%d power on\n", phy);
> -	}
>  
>  	/* Program PLL Rcomp code offset */
>  	val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
> -- 
> 2.13.2
> 
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-- 
Ville Syrjälä
Intel OTC
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