From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [RFC,4/6] dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit From: Vinod Koul Message-Id: <20180411091102.GZ6014@localhost> Date: Wed, 11 Apr 2018 14:41:03 +0530 To: Radhey Shyam Pandey Cc: dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, radheys@xilinx.com, lars@metafoo.de, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org List-ID: T24gTW9uLCBBcHIgMDIsIDIwMTggYXQgMDQ6MDk6MDRQTSArMDUzMCwgUmFkaGV5IFNoeWFtIFBh bmRleSB3cm90ZToKPiBBWElETUEgSVAgc2V0cyBjb21wbGV0aW9uIGJpdCB0byAxIHdoZW4gdGhl IHRyYW5zZmVyIGlzIGNvbXBsZXRlZC4gUmVhZAo+IHRoaXMgYml0IHRvIG1vdmUgZGVzY3JpcHRv ciBmcm9tIGFjdGl2ZSBsaXN0IHRvIHRoZSBkb25lIGxpc3QuIFRoaXMgZmVhdHVyZQo+IGlzIG5l ZWRlZCB3aGVuIGludGVycnVwdCBkZWxheSB0aW1lb3V0IGFuZCBJUlFUaHJlc2hvbGQgaXMgZW5h YmxlZCBpLmUKPiBEbHlfSXJxRW4gaXMgdHJpZ2dlcmVkIHcvbyBjb21wbGV0aW5nIEludGVycnVw dCBUaHJlc2hvbGQuCj4gCj4gU2lnbmVkLW9mZi1ieTogUmFkaGV5IFNoeWFtIFBhbmRleSA8cmFk aGV5c0B4aWxpbnguY29tPgo+IC0tLQo+ICBkcml2ZXJzL2RtYS94aWxpbngveGlsaW54X2RtYS5j IHwgICAxOCArKysrKysrKysrKysrKy0tLS0KPiAgMSBmaWxlcyBjaGFuZ2VkLCAxNCBpbnNlcnRp b25zKCspLCA0IGRlbGV0aW9ucygtKQo+IAo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2RtYS94aWxp bngveGlsaW54X2RtYS5jIGIvZHJpdmVycy9kbWEveGlsaW54L3hpbGlueF9kbWEuYwo+IGluZGV4 IDM2ZTFhYjkuLjUxODQ2NWUgMTAwNjQ0Cj4gLS0tIGEvZHJpdmVycy9kbWEveGlsaW54L3hpbGlu eF9kbWEuYwo+ICsrKyBiL2RyaXZlcnMvZG1hL3hpbGlueC94aWxpbnhfZG1hLmMKPiBAQCAtMTAz LDYgKzEwMyw3IEBACj4gICNkZWZpbmUgWElMSU5YX0RNQV9QQVJLX1BUUl9SRF9SRUZfU0hJRlQJ MAo+ICAjZGVmaW5lIFhJTElOWF9ETUFfUEFSS19QVFJfUkRfUkVGX01BU0sJCUdFTk1BU0soNCwg MCkKPiAgI2RlZmluZSBYSUxJTlhfRE1BX1JFR19WRE1BX1ZFUlNJT04JCTB4MDAyYwo+ICsjZGVm aW5lIFhJTElOWF9ETUFfQ09NUF9NQVNLCQkJQklUKDMxKQo+ICAKPiAgLyogUmVnaXN0ZXIgRGly ZWN0IE1vZGUgUmVnaXN0ZXJzICovCj4gICNkZWZpbmUgWElMSU5YX0RNQV9SRUdfVlNJWkUJCQkw eDAwMDAKPiBAQCAtMTM4NywxNiArMTM4OCwyNSBAQCBzdGF0aWMgdm9pZCB4aWxpbnhfZG1hX2lz c3VlX3BlbmRpbmcoc3RydWN0IGRtYV9jaGFuICpkY2hhbikKPiAgc3RhdGljIHZvaWQgeGlsaW54 X2RtYV9jb21wbGV0ZV9kZXNjcmlwdG9yKHN0cnVjdCB4aWxpbnhfZG1hX2NoYW4gKmNoYW4pCj4g IHsKPiAgCXN0cnVjdCB4aWxpbnhfZG1hX3R4X2Rlc2NyaXB0b3IgKmRlc2MsICpuZXh0Owo+ICsJ c3RydWN0IHhpbGlueF9heGlkbWFfdHhfc2VnbWVudCAqc2VnOwo+ICAKPiAgCS8qIFRoaXMgZnVu Y3Rpb24gd2FzIGludm9rZWQgd2l0aCBsb2NrIGhlbGQgKi8KPiAgCWlmIChsaXN0X2VtcHR5KCZj aGFuLT5hY3RpdmVfbGlzdCkpCj4gIAkJcmV0dXJuOwo+ICAKPiAgCWxpc3RfZm9yX2VhY2hfZW50 cnlfc2FmZShkZXNjLCBuZXh0LCAmY2hhbi0+YWN0aXZlX2xpc3QsIG5vZGUpIHsKPiAtCQlsaXN0 X2RlbCgmZGVzYy0+bm9kZSk7Cj4gLQkJaWYgKCFkZXNjLT5jeWNsaWMpCj4gLQkJCWRtYV9jb29r aWVfY29tcGxldGUoJmRlc2MtPmFzeW5jX3R4KTsKPiAtCQlsaXN0X2FkZF90YWlsKCZkZXNjLT5u b2RlLCAmY2hhbi0+ZG9uZV9saXN0KTsKPiArCj4gKwkJc2VnID0gbGlzdF9sYXN0X2VudHJ5KCZk ZXNjLT5zZWdtZW50cywKPiArCQkJCSAgICAgIHN0cnVjdCB4aWxpbnhfYXhpZG1hX3R4X3NlZ21l bnQsIG5vZGUpOwo+ICsJCWlmICgoc2VnLT5ody5zdGF0dXMgJiBYSUxJTlhfRE1BX0NPTVBfTUFT SykgfHwKPiArCQkJKCFjaGFuLT54ZGV2LT5oYXNfYXhpZXRoX2Nvbm5lY3RlZCkpIHsKCndoeSB0 aGUgc2Vjb25kIGNhc2UgPyBUaGF0IGlzIG5vdCBleHBhbGluZWQgaW4gbG9nPwoKPiArCQkJbGlz dF9kZWwoJmRlc2MtPm5vZGUpOwo+ICsJCQlpZiAoIWRlc2MtPmN5Y2xpYykKPiArCQkJCWRtYV9j b29raWVfY29tcGxldGUoJmRlc2MtPmFzeW5jX3R4KTsKPiArCQkJbGlzdF9hZGRfdGFpbCgmZGVz Yy0+bm9kZSwgJmNoYW4tPmRvbmVfbGlzdCk7Cj4gKwkJfSBlbHNlIHsKPiArCQkJYnJlYWs7Cj4g KwkJfQo+ICAJfQo+ICB9Cj4gIAo+IC0tIAo+IDEuNy4xCj4K From mboxrd@z Thu Jan 1 00:00:00 1970 From: vinod.koul@intel.com (Vinod Koul) Date: Wed, 11 Apr 2018 14:41:03 +0530 Subject: [RFC 4/6] dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit In-Reply-To: <1522665546-10035-5-git-send-email-radheys@xilinx.com> References: <1522665546-10035-1-git-send-email-radheys@xilinx.com> <1522665546-10035-5-git-send-email-radheys@xilinx.com> Message-ID: <20180411091102.GZ6014@localhost> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Mon, Apr 02, 2018 at 04:09:04PM +0530, Radhey Shyam Pandey wrote: > AXIDMA IP sets completion bit to 1 when the transfer is completed. Read > this bit to move descriptor from active list to the done list. This feature > is needed when interrupt delay timeout and IRQThreshold is enabled i.e > Dly_IrqEn is triggered w/o completing Interrupt Threshold. > > Signed-off-by: Radhey Shyam Pandey > --- > drivers/dma/xilinx/xilinx_dma.c | 18 ++++++++++++++---- > 1 files changed, 14 insertions(+), 4 deletions(-) > > diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c > index 36e1ab9..518465e 100644 > --- a/drivers/dma/xilinx/xilinx_dma.c > +++ b/drivers/dma/xilinx/xilinx_dma.c > @@ -103,6 +103,7 @@ > #define XILINX_DMA_PARK_PTR_RD_REF_SHIFT 0 > #define XILINX_DMA_PARK_PTR_RD_REF_MASK GENMASK(4, 0) > #define XILINX_DMA_REG_VDMA_VERSION 0x002c > +#define XILINX_DMA_COMP_MASK BIT(31) > > /* Register Direct Mode Registers */ > #define XILINX_DMA_REG_VSIZE 0x0000 > @@ -1387,16 +1388,25 @@ static void xilinx_dma_issue_pending(struct dma_chan *dchan) > static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan) > { > struct xilinx_dma_tx_descriptor *desc, *next; > + struct xilinx_axidma_tx_segment *seg; > > /* This function was invoked with lock held */ > if (list_empty(&chan->active_list)) > return; > > list_for_each_entry_safe(desc, next, &chan->active_list, node) { > - list_del(&desc->node); > - if (!desc->cyclic) > - dma_cookie_complete(&desc->async_tx); > - list_add_tail(&desc->node, &chan->done_list); > + > + seg = list_last_entry(&desc->segments, > + struct xilinx_axidma_tx_segment, node); > + if ((seg->hw.status & XILINX_DMA_COMP_MASK) || > + (!chan->xdev->has_axieth_connected)) { why the second case ? That is not expalined in log? > + list_del(&desc->node); > + if (!desc->cyclic) > + dma_cookie_complete(&desc->async_tx); > + list_add_tail(&desc->node, &chan->done_list); > + } else { > + break; > + } > } > } > > -- > 1.7.1 > -- ~Vinod From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752829AbeDKJGj (ORCPT ); Wed, 11 Apr 2018 05:06:39 -0400 Received: from mga05.intel.com ([192.55.52.43]:47854 "EHLO mga05.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751880AbeDKJGh (ORCPT ); Wed, 11 Apr 2018 05:06:37 -0400 X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,435,1517904000"; d="scan'208";a="215737110" Date: Wed, 11 Apr 2018 14:41:03 +0530 From: Vinod Koul To: Radhey Shyam Pandey Cc: dan.j.williams@intel.com, michal.simek@xilinx.com, appana.durga.rao@xilinx.com, radheys@xilinx.com, lars@metafoo.de, dmaengine@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [RFC 4/6] dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit Message-ID: <20180411091102.GZ6014@localhost> References: <1522665546-10035-1-git-send-email-radheys@xilinx.com> <1522665546-10035-5-git-send-email-radheys@xilinx.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1522665546-10035-5-git-send-email-radheys@xilinx.com> User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, Apr 02, 2018 at 04:09:04PM +0530, Radhey Shyam Pandey wrote: > AXIDMA IP sets completion bit to 1 when the transfer is completed. Read > this bit to move descriptor from active list to the done list. This feature > is needed when interrupt delay timeout and IRQThreshold is enabled i.e > Dly_IrqEn is triggered w/o completing Interrupt Threshold. > > Signed-off-by: Radhey Shyam Pandey > --- > drivers/dma/xilinx/xilinx_dma.c | 18 ++++++++++++++---- > 1 files changed, 14 insertions(+), 4 deletions(-) > > diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c > index 36e1ab9..518465e 100644 > --- a/drivers/dma/xilinx/xilinx_dma.c > +++ b/drivers/dma/xilinx/xilinx_dma.c > @@ -103,6 +103,7 @@ > #define XILINX_DMA_PARK_PTR_RD_REF_SHIFT 0 > #define XILINX_DMA_PARK_PTR_RD_REF_MASK GENMASK(4, 0) > #define XILINX_DMA_REG_VDMA_VERSION 0x002c > +#define XILINX_DMA_COMP_MASK BIT(31) > > /* Register Direct Mode Registers */ > #define XILINX_DMA_REG_VSIZE 0x0000 > @@ -1387,16 +1388,25 @@ static void xilinx_dma_issue_pending(struct dma_chan *dchan) > static void xilinx_dma_complete_descriptor(struct xilinx_dma_chan *chan) > { > struct xilinx_dma_tx_descriptor *desc, *next; > + struct xilinx_axidma_tx_segment *seg; > > /* This function was invoked with lock held */ > if (list_empty(&chan->active_list)) > return; > > list_for_each_entry_safe(desc, next, &chan->active_list, node) { > - list_del(&desc->node); > - if (!desc->cyclic) > - dma_cookie_complete(&desc->async_tx); > - list_add_tail(&desc->node, &chan->done_list); > + > + seg = list_last_entry(&desc->segments, > + struct xilinx_axidma_tx_segment, node); > + if ((seg->hw.status & XILINX_DMA_COMP_MASK) || > + (!chan->xdev->has_axieth_connected)) { why the second case ? That is not expalined in log? > + list_del(&desc->node); > + if (!desc->cyclic) > + dma_cookie_complete(&desc->async_tx); > + list_add_tail(&desc->node, &chan->done_list); > + } else { > + break; > + } > } > } > > -- > 1.7.1 > -- ~Vinod