From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from userp2120.oracle.com ([156.151.31.85]) by Galois.linutronix.de with esmtps (TLS1.2:RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1f8ns8-0002bp-VP for speck@linutronix.de; Wed, 18 Apr 2018 16:15:46 +0200 Received: from pps.filterd (userp2120.oracle.com [127.0.0.1]) by userp2120.oracle.com (8.16.0.22/8.16.0.22) with SMTP id w3IEBSHa129172 for ; Wed, 18 Apr 2018 14:15:38 GMT Received: from aserv0022.oracle.com (aserv0022.oracle.com [141.146.126.234]) by userp2120.oracle.com with ESMTP id 2hdrxp2usw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Wed, 18 Apr 2018 14:15:38 +0000 Received: from userv0122.oracle.com (userv0122.oracle.com [156.151.31.75]) by aserv0022.oracle.com (8.14.4/8.14.4) with ESMTP id w3IEFbpj025586 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Wed, 18 Apr 2018 14:15:37 GMT Received: from abhmp0006.oracle.com (abhmp0006.oracle.com [141.146.116.12]) by userv0122.oracle.com (8.14.4/8.14.4) with ESMTP id w3IEFakJ003538 for ; Wed, 18 Apr 2018 14:15:36 GMT Message-Id: <20180413022649.214912659@localhost.localdomain> Date: Thu, 12 Apr 2018 22:26:49 -0400 From: konrad.wilk@oracle.com Subject: [MODERATED] [patch 0/8] MDD v1.3.1 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 To: speck@linutronix.de List-ID: Since v3: - Fixed the bug where IBRS was enabled when going in the kernel. - Untangled two patches. Couple of things: - 'Memory disambiguation disable mitigation is enabled' sounds horrible. I ended up picking up for sysfs 'md' and for x86 speaking about 'mdd' and putting the parameters around the 'disable' part. - No AMD SVM support as I don't know the bits. - The last two patches are crap. I should have used the latest one from Tim Chen, but it may be an academic point as folks may just decide that having this memory disambiguation being enabled/disabled when switching between kernel and userspace is not worth it. - It works nicely. Documentation/admin-guide/kernel-parameters.txt | 11 +++ arch/x86/entry/entry_64.S | 14 ++- arch/x86/entry/entry_64_compat.S | 7 ++ arch/x86/include/asm/cpufeatures.h | 3 + arch/x86/include/asm/msr-index.h | 1 + arch/x86/include/asm/nospec-branch.h | 103 +++++++++++++++++++- arch/x86/kernel/cpu/bugs.c | 119 ++++++++++++++++++++++++ arch/x86/kernel/cpu/common.c | 20 ++++ arch/x86/kernel/cpu/intel.c | 1 + arch/x86/kvm/cpuid.c | 2 +- arch/x86/kvm/vmx.c | 14 +-- drivers/base/cpu.c | 8 ++ include/linux/cpu.h | 2 + 13 files changed, 293 insertions(+), 12 deletions(-) Konrad Rzeszutek Wilk (7): x86/mdd: Expose the /sys/../md and BUG_MD x86/mdd: Provide boot parameters to select which MD mitigation to use. x86/mdd: If MD is disabled at bootup, then set the SPEC_CTRL MSR. x86/mdd/firmware calls: Save/Restore the MDD bit when using SPEC_CTRL x86/mdd/KVM: Support the combination of guest IBRS and ours. x86/mdd: Add [ENABLE|DISABLE]_SPEC_CTRL_[|CLOBBER] and variants. x86/mdd: Add SPEC_CTRL macros on system call/interrupts/exceptions/etc