From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [RFC,4/6] dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit From: Vinod Koul Message-Id: <20180423052317.GZ6014@localhost> Date: Mon, 23 Apr 2018 10:53:17 +0530 To: Radhey Shyam Pandey Cc: "dan.j.williams@intel.com" , "michal.simek@xilinx.com" , Appana Durga Kedareswara Rao , "lars@metafoo.de" , "dmaengine@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "'RADHEYCS@GMAIL.COM'" List-ID: T24gVHVlLCBBcHIgMTcsIDIwMTggYXQgMTI6Mjg6NTJQTSArMDAwMCwgUmFkaGV5IFNoeWFtIFBh bmRleSB3cm90ZToKCj4gPiA+ICsJCWlmICgoc2VnLT5ody5zdGF0dXMgJiBYSUxJTlhfRE1BX0NP TVBfTUFTSykgfHwKPiA+ID4gKwkJCSghY2hhbi0+eGRldi0+aGFzX2F4aWV0aF9jb25uZWN0ZWQp KSB7Cj4gPiAKPiA+IHdoeSB0aGUgc2Vjb25kIGNhc2UgPyBUaGF0IGlzIG5vdCBleHBhbGluZWQg aW4gbG9nPwo+IEluIHRoZSBjdXJyZW50IGltcGxlbWVudGF0aW9uLCBkZWxheSB0aW1lb3V0IGlz IGVuYWJsZWQgb25seSBmb3IKPiBoYXNfYXhpZXRoX2Nvbm5lY3RlZCB1c2VjYXNlLiBGb3IgZXRo ZXJuZXQsIHdlIG5lZWQgcmVhbC10aW1lIHByb2Nlc3NpbmcKPiB3aGlsZSBzdGlsbCBoYXZpbmcg YmVuZWZpdCBvZiBpbnRlcnJ1cHQgY29hbGVzY2luZy4gRXhhbXBsZTogSW4gUlggaW50ZXJydXB0 Cj4gY29hbGVzY2luZyBpcyBzZXQgdG8gMHgzLiAgV2l0aG91dCBkZWxheSB0aW1lb3V0LCBETUEg ZW5naW5lIHdpbGwgd2FpdCBmb3IKPiBhbGwgZnJhbWVzIGFuZCB0aGVuIGlzc3VlIGNvbXBsZXRp b24gaW50ZXJydXB0LiBJbiBldGhlcm5ldCB1c2VjYXNlLCB0aGlzCj4gY2FuIGludHJvZHVjZSBo dWdlIGxhdGVuY2llcy4gRGVsYXkgdGltZW91dCBpbnRlcnJ1cHQgd2lsbCB0cmlnZ2VyIGlmIGRl bGF5Cj4gdGltZSBwZXJpb2QgaGFzIGV4cGlyZWQgYW5kIHdlIGNhbiBub3RpZnkgZG1hIGNsaWVu dCB3aXRoIHJlY2VpdmVkIGZyYW1lcy4KPiAKPiBUaGUgc2Vjb25kIGNhc2UgaXMgYWRkZWQgdG8g a2VlcCB0aGUgcHJldmlvdXMgaW1wbGVtZW50YXRpb24gYXMgaXMuKGkuZSB3aGVuCj4gRGVsYXkg dGltZW91dCBpbnRlcnJ1cHQgaXMgbm90IGVuYWJsZWQgLSBtb3ZlIGFsbCBhY3RpdmUgZGVzYyB0 byBkb25lIGxpc3QpLiAKPiBTdXJlIEkgd2lsbCBhZGQgYSBkZXNjcmlwdGlvbiBmb3IgaXQgaW4g dGhlIGNvbW1pdCBsb2cuCgpUaGF0IHNob3VsZCBoZWxwLCBpdCBkaWRuJ3Qgc2VlbSB0byBoYXZl IGFueXRoaW5nIHRvIGRvIHdpdGggbG9nIG9yIG90aGVyCmNoYW5nZXMsIHBsZWFzZSBrZWVwIGlu IG1pbmQgYWdhaW4gdGhhdCBjaGFuZ2Vsb2cgc2hvdWxkIGRlc2NyaWJlIHRoZSBjaGFuZ2UKYW5k IGhlbHAgcHBsIHJldmlldy4uLgo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: vinod.koul@intel.com (Vinod Koul) Date: Mon, 23 Apr 2018 10:53:17 +0530 Subject: [RFC 4/6] dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit In-Reply-To: References: <1522665546-10035-1-git-send-email-radheys@xilinx.com> <1522665546-10035-5-git-send-email-radheys@xilinx.com> <20180411091102.GZ6014@localhost> Message-ID: <20180423052317.GZ6014@localhost> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Tue, Apr 17, 2018 at 12:28:52PM +0000, Radhey Shyam Pandey wrote: > > > + if ((seg->hw.status & XILINX_DMA_COMP_MASK) || > > > + (!chan->xdev->has_axieth_connected)) { > > > > why the second case ? That is not expalined in log? > In the current implementation, delay timeout is enabled only for > has_axieth_connected usecase. For ethernet, we need real-time processing > while still having benefit of interrupt coalescing. Example: In RX interrupt > coalescing is set to 0x3. Without delay timeout, DMA engine will wait for > all frames and then issue completion interrupt. In ethernet usecase, this > can introduce huge latencies. Delay timeout interrupt will trigger if delay > time period has expired and we can notify dma client with received frames. > > The second case is added to keep the previous implementation as is.(i.e when > Delay timeout interrupt is not enabled - move all active desc to done list). > Sure I will add a description for it in the commit log. That should help, it didn't seem to have anything to do with log or other changes, please keep in mind again that changelog should describe the change and help ppl review... -- ~Vinod From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751392AbeDWFSm (ORCPT ); Mon, 23 Apr 2018 01:18:42 -0400 Received: from mga14.intel.com ([192.55.52.115]:14688 "EHLO mga14.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750786AbeDWFSk (ORCPT ); Mon, 23 Apr 2018 01:18:40 -0400 X-Amp-Result: UNKNOWN X-Amp-Original-Verdict: FILE UNKNOWN X-Amp-File-Uploaded: False X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.49,316,1520924400"; d="scan'208";a="222540900" Date: Mon, 23 Apr 2018 10:53:17 +0530 From: Vinod Koul To: Radhey Shyam Pandey Cc: "dan.j.williams@intel.com" , "michal.simek@xilinx.com" , Appana Durga Kedareswara Rao , "lars@metafoo.de" , "dmaengine@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "'RADHEYCS@GMAIL.COM'" Subject: Re: [RFC 4/6] dmaengine: xilinx_dma: Freeup active list based on descriptor completion bit Message-ID: <20180423052317.GZ6014@localhost> References: <1522665546-10035-1-git-send-email-radheys@xilinx.com> <1522665546-10035-5-git-send-email-radheys@xilinx.com> <20180411091102.GZ6014@localhost> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.5.24 (2015-08-30) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Apr 17, 2018 at 12:28:52PM +0000, Radhey Shyam Pandey wrote: > > > + if ((seg->hw.status & XILINX_DMA_COMP_MASK) || > > > + (!chan->xdev->has_axieth_connected)) { > > > > why the second case ? That is not expalined in log? > In the current implementation, delay timeout is enabled only for > has_axieth_connected usecase. For ethernet, we need real-time processing > while still having benefit of interrupt coalescing. Example: In RX interrupt > coalescing is set to 0x3. Without delay timeout, DMA engine will wait for > all frames and then issue completion interrupt. In ethernet usecase, this > can introduce huge latencies. Delay timeout interrupt will trigger if delay > time period has expired and we can notify dma client with received frames. > > The second case is added to keep the previous implementation as is.(i.e when > Delay timeout interrupt is not enabled - move all active desc to done list). > Sure I will add a description for it in the commit log. That should help, it didn't seem to have anything to do with log or other changes, please keep in mind again that changelog should describe the change and help ppl review... -- ~Vinod