From mboxrd@z Thu Jan 1 00:00:00 1970 From: shawnguo@kernel.org (Shawn Guo) Date: Mon, 23 Apr 2018 16:44:56 +0800 Subject: [PATCH v3 5/6] ARM: dts: Add support for emtrion emCON-MX6 series In-Reply-To: <20180420125108.14197-6-jan.tuerk@emtrion.com> References: <20171220134710.64479-2-jan.tuerk@emtrion.com> <20180420125108.14197-1-jan.tuerk@emtrion.com> <20180420125108.14197-6-jan.tuerk@emtrion.com> Message-ID: <20180423084454.GZ25429@dragon> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Fri, Apr 20, 2018 at 02:50:52PM +0200, jan.tuerk at emtrion.com wrote: > From: Jan Tuerk > > This patch adds support for the emtrion GmbH emCON-MX6 modules. > They are available with imx.6 Solo, Dual-Lite, Dual and Quad > equipped with Memory from 512MB to 2GB (configured by U-Boot). > > Our default developer-Kit ships with the Avari baseboard and the > EDT ETM0700G0BDH6 Display (imx6[q|dl]-emcon-avari). > > The devicetree is split into the common part providing all module > components and the basic support for all SoC versions > (imx6qdl-emcon.dtsi) and parts which are i.mx6 S|DL and D|Q relevant. > Finally the support for the avari baseboard in the developer-kit > configuration is provided by the emcon-avari dts files. > > Signed-off-by: Jan Tuerk > --- > Documentation/devicetree/bindings/arm/emtrion.txt | 13 + It's better to have a separate patch for bindings doc, which needs to be acknowledged by DT maintainers. > arch/arm/boot/dts/Makefile | 2 + > arch/arm/boot/dts/imx6dl-emcon-avari.dts | 224 ++++++ > arch/arm/boot/dts/imx6dl-emcon.dtsi | 27 + > arch/arm/boot/dts/imx6q-emcon-avari.dts | 224 ++++++ > arch/arm/boot/dts/imx6q-emcon.dtsi | 27 + > arch/arm/boot/dts/imx6qdl-emcon.dtsi | 838 ++++++++++++++++++++++ > 7 files changed, 1355 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/emtrion.txt > create mode 100644 arch/arm/boot/dts/imx6dl-emcon-avari.dts > create mode 100644 arch/arm/boot/dts/imx6dl-emcon.dtsi > create mode 100644 arch/arm/boot/dts/imx6q-emcon-avari.dts > create mode 100644 arch/arm/boot/dts/imx6q-emcon.dtsi > create mode 100644 arch/arm/boot/dts/imx6qdl-emcon.dtsi > > diff --git a/Documentation/devicetree/bindings/arm/emtrion.txt b/Documentation/devicetree/bindings/arm/emtrion.txt > new file mode 100644 > index 000000000000..3ff6c6c2034d > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/emtrion.txt > @@ -0,0 +1,13 @@ > +Emtrion Devicetree Bindings > +=========================== > + > +emCON Series: > +------------- > + > +Required root node properties > + - compatible: > + - "emtrion,emcon-mx6", "fsl,imx6q", "fsl,imx6dl"; : emCON-MX6 Generic SoM > + - "emtrion,emcon-mx6", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM > + - "emtrion,emcon-mx6-avari", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM on Avari Base > + - "emtrion,emcon-mx6", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM > + - "emtrion,emcon-mx6-avari", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM on Avari Base > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index 7e2424957809..05b930da3fda 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -381,6 +381,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ > imx6dl-cubox-i-emmc-som-v15.dtb \ > imx6dl-cubox-i-som-v15.dtb \ > imx6dl-dfi-fs700-m60.dtb \ > + imx6dl-emcon-avari.dtb \ > imx6dl-gw51xx.dtb \ > imx6dl-gw52xx.dtb \ > imx6dl-gw53xx.dtb \ > @@ -442,6 +443,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ > imx6q-display5-tianma-tm070-1280x768.dtb \ > imx6q-dmo-edmqmx6.dtb \ > imx6q-dms-ba16.dtb \ > + imx6q-emcon-avari.dtb \ > imx6q-evi.dtb \ > imx6q-gk802.dtb \ > imx6q-gw51xx.dtb \ > diff --git a/arch/arm/boot/dts/imx6dl-emcon-avari.dts b/arch/arm/boot/dts/imx6dl-emcon-avari.dts > new file mode 100644 > index 000000000000..2344fb9498e3 > --- /dev/null > +++ b/arch/arm/boot/dts/imx6dl-emcon-avari.dts > @@ -0,0 +1,224 @@ > +// SPDX-License-Identifier: (GPL-2.0 or MIT) > +/* Copyright (C) 2018 emtrion GmbH > + * Author: Jan Tuerk > + */ /* * Copyright ... */ > + > +/dts-v1/; > +#include "imx6dl.dtsi" > +#include "imx6qdl-emcon.dtsi" > +#include "imx6dl-emcon.dtsi" /*Include camera2 pinmux*/ /* bla bla */ > + > +/ { > + model = "emtrion SoM emCON-MX6 Solo/Dual-Lite Avari"; > + compatible = "emtrion,emcon-mx6-avari", "fsl,imx6dl"; > + > + aliases { > + mmc0 = &usdhc3; > + mmc2 = &usdhc1; > + mmc1 = &usdhc2; > + mmc3 = &usdhc4; > + }; > + > + chosen { > + stdout-path = <&uart1>; > + }; > + > + memory { The unit-address is missing. > + reg = <0x10000000 0x40000000>; > + }; > + > + supplies { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <0>; DT maintainers do not like this fake container node. Please put the fixed regulator nodes directly under root with a unique name like below. reg_xxx: regulator-xxx { ... }; > + > + wallplug5p0: supply at 0 { > + compatible = "regulator-fixed"; > + reg = <0>; > + regulator-name = "WALL-PLUG"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + regulator-always-on; > + regulator-boot-on; > + }; > + > + base3p3: supply at 1 { > + compatible = "regulator-fixed"; > + reg = <1>; > + vin-supply = <&wallplug5p0>; > + regulator-name = "3V3-avari"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-always-on; > + regulator-boot-on; > + }; > + > + base1p5: supply at 2 { > + compatible = "regulator-fixed"; > + reg = <2>; > + vin-supply = <&base3p3>; > + regulator-name = "1V5-avari"; > + regulator-min-microvolt = <1500000>; > + regulator-max-microvolt = <1500000>; > + regulator-always-on; > + regulator-boot-on; > + }; > + > + reg_usb_otg: otgvbus at 3 { > + compatible = "regulator-fixed"; > + reg = <3>; > + vin-supply = <&wallplug5p0>; > + regulator-name = "OTG_VBUS"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; > + regulator-always-on; > + }; > + > + }; > + > + > + sndosc: 12MHZosc { clock-xxx { ... }; > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <12000000>; > + }; > + > + sound { > + compatible = "fsl,imx-audio-sgtl5000"; > + model = "emCON-avari-sgtl5000"; > + ssi-controller = <&ssi2>; > + audio-codec = <&sgtl5000>; > + audio-routing = > + "Headphone Jack", "HP_OUT"; > + mux-int-port = <2>; > + mux-ext-port = <3>; > + }; > + > +}; > + > + One newline is good enough. > +&iomuxc { > + pinctrl-names = "default"; > + /*Unused emCON-MX6 outputs on AVARI*/ > + pinctrl-0 = < > + &pinctrl_emcon_gpio1 &pinctrl_emcon_gpio2 > + &pinctrl_emcon_gpio3 &pinctrl_emcon_gpio5 > + &pinctrl_emcon_gpio6 &pinctrl_emcon_gpio7 > + &pinctrl_emcon_gpio8 &pinctrl_emcon_irq_a > + &pinctrl_emcon_irq_b &pinctrl_emcon_irq_c > + &pinctrl_emcon_irq_pwr &pinctrl_nor_flash > + &pinctrl_usdhc2 > + &pinctrl_spdif_out &pinctrl_spdif_in > + &pinctrl_cpi1 &pinctrl_cpi2 > + >; Only pins without clear consumer should be put into hog group. Also the indent seems broken. > +}; > + > +&audmux { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_audmux>; > + status = "okay"; > +}; > + > + > + One newline is good enough. Also, please try to sort these labelled nodes alphabetically. > +&i2c3 { > + clock-frequency = <100000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c3>; > + status = "okay"; > + > + sgtl5000: audio-codec at a { > + compatible = "fsl,sgtl5000"; > + reg = <0x0a>; > + clocks = <&sndosc>; > + VDDA-supply = <&base3p3>; > + VDDIO-supply = <&base3p3>; #sound-dai-cells is missing. > + }; > + > + boardID: pca8754a at 3a { Please find a more generic node name for it. > + compatible = "nxp,pca8574"; > + reg = <0x3a>; > + gpio-controller; > + #gpio-cells = <1>; > + }; > + > + captouch: touchscreen at 38 { > + compatible = "edt,edt-ft5406"; > + reg = <0x38>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_irq_touch2 &pinctrl_emcon_gpio4>; > + interrupt-parent = <&gpio6>; > + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; > + wake-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; > + wakeup-source; > + status = "okay"; The "okay" status is only needed to flip the default "disabled" device. > + }; > +}; > + > +&ssi2 { > + status = "okay"; > +}; > + > +&rgb_encoder { > + status = "okay"; > +}; > + > +&rgb_panel { > + compatible = "edt,etm0700g0bdh6"; > + status = "okay"; > +}; > + > +&i2c2 { > + status = "okay"; > +}; > + > +&hdmi { > + ddc-i2c-bus = <&i2c2>; > + status = "okay"; > +}; > + > +&usbh1 { > + status = "okay"; > +}; > + > +&usbotg { > + status = "okay"; > +}; > + > +&pcie { > + status = "okay"; > +}; > + > +&usdhc1 { > + status = "okay"; > +}; > + > +&can1 { > + status = "okay"; > +}; > + > +&can2 { > + status = "okay"; > +}; > + > +&uart2 { > + status = "okay"; > + uart-has-rtscts; > +}; > + > +&uart3 { > + status = "okay"; > +}; > + > +&uart4 { > + status = "okay"; > +}; > + > +&uart5 { > + status = "okay"; > +}; > + > +&ecspi2 { > + status = "okay"; > +}; > diff --git a/arch/arm/boot/dts/imx6dl-emcon.dtsi b/arch/arm/boot/dts/imx6dl-emcon.dtsi > new file mode 100644 > index 000000000000..1ed629c9747e > --- /dev/null > +++ b/arch/arm/boot/dts/imx6dl-emcon.dtsi > @@ -0,0 +1,27 @@ > +// SPDX-License-Identifier: (GPL-2.0 or MIT) > +/* Copyright (C) 2018 emtrion GmbH > + * Author: Jan Tuerk > + */ > + > +/ { > + model = "emtrion SoM emCON-MX6 Solo/DualLite"; > + compatible = "emtrion,emcon-mx6", "fsl,imx6dl"; > +}; > + > +&iomuxc { > + pinctrl_cpi2: csi1grp { > + fsl,pins = < > + MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0x0b0b1 > + MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b1 > + MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b1 > + MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b1 > + MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b1 > + MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b1 > + MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b1 > + MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b1 > + MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b1 > + MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b1 > + MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b1 > + >; > + }; > +}; > diff --git a/arch/arm/boot/dts/imx6q-emcon-avari.dts b/arch/arm/boot/dts/imx6q-emcon-avari.dts > new file mode 100644 > index 000000000000..0c85b5ee011c > --- /dev/null > +++ b/arch/arm/boot/dts/imx6q-emcon-avari.dts There are so many things duplicated between imx6dl-emcon-avari.dts and imx6q-emcon-avari.dts. Can you do something to avoid that? > @@ -0,0 +1,224 @@ > +// SPDX-License-Identifier: (GPL-2.0 or MIT) > +/* Copyright (C) 2018 emtrion GmbH > + * Author: Jan Tuerk > + */ > + > +/dts-v1/; > +#include "imx6q.dtsi" > +#include "imx6qdl-emcon.dtsi" > +#include "imx6q-emcon.dtsi" /*Include camera2 pinmux*/ > + > +/ { > + model = "emtrion SoM emCON-MX6 Dual/Quad on Avari"; > + compatible = "emtrion,emcon-mx6-avari", "fsl,imx6q"; > + > + aliases { > + mmc0 = &usdhc3; > + mmc2 = &usdhc1; > + mmc1 = &usdhc2; > + mmc3 = &usdhc4; > + }; > + > + chosen { > + stdout-path = <&uart1>; > + }; > + > + memory { > + reg = <0x10000000 0x40000000>; > + }; > + > + supplies { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <0>; > + > + wallplug5p0: supply at 0 { > + compatible = "regulator-fixed"; > + reg = <0>; > + regulator-name = "WALL-PLUG"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + regulator-always-on; > + regulator-boot-on; > + }; > + > + base3p3: supply at 1 { > + compatible = "regulator-fixed"; > + reg = <1>; > + vin-supply = <&wallplug5p0>; > + regulator-name = "3V3-avari"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-always-on; > + regulator-boot-on; > + }; > + > + base1p5: supply at 2 { > + compatible = "regulator-fixed"; > + reg = <2>; > + vin-supply = <&base3p3>; > + regulator-name = "1V5-avari"; > + regulator-min-microvolt = <1500000>; > + regulator-max-microvolt = <1500000>; > + regulator-always-on; > + regulator-boot-on; > + }; > + > + reg_usb_otg: otgvbus at 3 { > + compatible = "regulator-fixed"; > + reg = <3>; > + vin-supply = <&wallplug5p0>; > + regulator-name = "OTG_VBUS"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; > + regulator-always-on; > + }; > + > + }; > + > + > + sndosc: 12MHZosc { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <12000000>; > + }; > + > + sound { > + compatible = "fsl,imx-audio-sgtl5000"; > + model = "emCON-avari-sgtl5000"; > + ssi-controller = <&ssi2>; > + audio-codec = <&sgtl5000>; > + audio-routing = > + "Headphone Jack", "HP_OUT"; > + mux-int-port = <2>; > + mux-ext-port = <3>; > + }; > + > +}; > + > + > +&iomuxc { > + pinctrl-names = "default"; > + /*Unused emCON-MX6 pingroups on AVARI baseboard, enable defaults*/ > + pinctrl-0 = < > + &pinctrl_emcon_gpio1 &pinctrl_emcon_gpio2 > + &pinctrl_emcon_gpio3 &pinctrl_emcon_gpio5 > + &pinctrl_emcon_gpio6 &pinctrl_emcon_gpio7 > + &pinctrl_emcon_gpio8 &pinctrl_emcon_irq_a > + &pinctrl_emcon_irq_b &pinctrl_emcon_irq_c > + &pinctrl_emcon_irq_pwr &pinctrl_nor_flash > + &pinctrl_usdhc2 > + &pinctrl_spdif_out &pinctrl_spdif_in > + &pinctrl_cpi1 &pinctrl_cpi2 > + >; > +}; > + > +&audmux { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_audmux>; > + status = "okay"; > +}; > + > + > + > +&i2c3 { > + clock-frequency = <100000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c3>; > + status = "okay"; > + > + sgtl5000: audio-codec at a { > + compatible = "fsl,sgtl5000"; > + reg = <0x0a>; > + clocks = <&sndosc>; > + VDDA-supply = <&base3p3>; > + VDDIO-supply = <&base3p3>; > + }; > + > + boardID: pca8754a at 3a { > + compatible = "nxp,pca8574"; > + reg = <0x3a>; > + gpio-controller; > + #gpio-cells = <1>; > + }; > + > + captouch: touchscreen at 38 { > + compatible = "edt,edt-ft5406"; > + reg = <0x38>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_irq_touch2 &pinctrl_emcon_gpio4>; > + interrupt-parent = <&gpio6>; > + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; > + wake-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; > + wakeup-source; > + status = "okay"; > + }; > +}; > + > +&ssi2 { > + status = "okay"; > +}; > + > +&rgb_encoder { > + status = "okay"; > +}; > + > +&rgb_panel { > + compatible = "edt,etm0700g0bdh6"; > + status = "okay"; > +}; > + > +&i2c2 { > + status = "okay"; > +}; > + > +&hdmi { > + ddc-i2c-bus = <&i2c2>; > + status = "okay"; > +}; > + > +&usbh1 { > + status = "okay"; > +}; > + > +&usbotg { > + status = "okay"; > +}; > + > +&pcie { > + status = "okay"; > +}; > + > +&usdhc1 { > + status = "okay"; > +}; > + > +&can1 { > + status = "okay"; > +}; > + > +&can2 { > + status = "okay"; > +}; > + > +&uart2 { > + status = "okay"; > + uart-has-rtscts; > +}; > + > +&uart3 { > + status = "okay"; > +}; > + > +&uart4 { > + status = "okay"; > +}; > + > +&uart5 { > + status = "okay"; > +}; > + > +&ecspi2 { > + status = "okay"; > +}; > diff --git a/arch/arm/boot/dts/imx6q-emcon.dtsi b/arch/arm/boot/dts/imx6q-emcon.dtsi > new file mode 100644 > index 000000000000..33b3fbf3fba0 > --- /dev/null > +++ b/arch/arm/boot/dts/imx6q-emcon.dtsi > @@ -0,0 +1,27 @@ > +// SPDX-License-Identifier: (GPL-2.0 or MIT) > +/* Copyright (C) 2018 emtrion GmbH > + * Author: Jan Tuerk > + */ > + > +/ { > + model = "emtrion SoM emCON-MX6 Dual/Quad"; > + compatible = "emtrion,emcon-mx6", "fsl,imx6q"; > +}; > + > +&iomuxc { > + pinctrl_cpi2: csi1grp { > + fsl,pins = < > + MX6QDL_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x0b0b1 > + MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b1 > + MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b1 > + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b1 > + MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b1 > + MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b1 > + MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b1 > + MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b1 > + MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b1 > + MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b1 > + MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b1 > + >; > + }; > +}; > diff --git a/arch/arm/boot/dts/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/imx6qdl-emcon.dtsi > new file mode 100644 > index 000000000000..5f9296dce130 > --- /dev/null > +++ b/arch/arm/boot/dts/imx6qdl-emcon.dtsi > @@ -0,0 +1,838 @@ > +// SPDX-License-Identifier: (GPL-2.0 or MIT) > +/* Copyright (C) 2018 emtrion GmbH > + * Author: Jan Tuerk > + */ > + > +#include > +#include > +#include > + > +/ { > + > + model = "emtrion SoM emCON-MX6"; > + compatible = "emtrion,emcon-mx6", "fsl,imx6q", "fsl,imx6dl"; > + > + aliases { > + mmc0 = &usdhc3; > + mmc2 = &usdhc1; > + mmc1 = &usdhc2; > + }; > + > + regulators { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <0>; > + > + reg_parallel_disp: regulator at 0 { > + compatible = "regulator-fixed"; > + reg = <0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_rgb_bl_en>; > + regulator-name = "LCD-Supply"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + gpio = <&gpio7 9 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + }; > + > + reg_lvds_disp: regulator at 1 { > + compatible = "regulator-fixed"; > + reg = <1>; > + regulator-name = "LVDS-Supply"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + gpio = <&gpio7 10 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + }; > + }; > + > + som_leds: leds { > + compatible = "gpio-leds"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_som_leds>; > + > + green { > + label = "som:green"; > + gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; > + linux,default-trigger = "heartbeat"; > + default-state = "on"; > + }; > + > + red { > + label = "som:red"; > + gpios = <&gpio3 1 GPIO_ACTIVE_LOW>; > + default-state = "keep"; > + }; > + > + }; > + > + gpio-keys { > + compatible = "gpio-keys"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_emcon_wake>; > + > + wake { > + label = "Wake"; > + linux,code = ; > + gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; > + wakeup-source; > + }; > + }; > + > + pwm_fan: pwm-fan { > + compatible = "pwm-fan"; > + cooling-min-state = <0>; > + cooling-max-state = <4>; > + #cooling-cells = <2>; > + pwms = <&pwm4 0 50000>; > + cooling-levels = <0 64 127 191 255>; > + status = "disabled"; > + }; > + > + rgb_encoder: disp0 { s/disp0/display > + compatible = "fsl,imx-parallel-display"; > + #address-cells = <1>; > + #size-cells = <0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_rgb24_display>; > + status = "disabled"; > + > + port at 0 { > + reg = <0>; Have a newline between property list and child node. > + rgb_encoder_in: endpoint { > + remote-endpoint = <&ipu1_di0_disp0>; > + }; > + }; > + > + port at 1 { > + reg = <1>; > + rgb_encoder_out: endpoint { > + remote-endpoint = <&rgb_panel_in>; > + }; > + }; > + }; > + > + rgb_panel: panel { > + backlight = <&rgb_backlight>; > + power-supply = <®_parallel_disp>; > + port { > + rgb_panel_in: endpoint { > + remote-endpoint = <&rgb_encoder_out>; > + }; > + }; > + }; > + > + rgb_backlight: rgb-backlight { > + compatible = "pwm-backlight"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_rgb_bl>; > + enable-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; > + pwms = <&pwm3 0 5000000>; > + brightness-levels = <250 176 160 144 128 112 > + 96 80 64 48 32 16 8 1 > + >; Broken indent. > + default-brightness-level = <13>; > + status = "okay"; > + }; > + > + lvds_backlight: lvds-backlight { > + compatible = "pwm-backlight"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_lvds_bl>; > + enable-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; > + pwms = <&pwm1 0 50000>; > + brightness-levels = <0 4 8 16 32 64 80 96 112 > + 128 144 160 176 250 > + >; > + default-brightness-level = <13>; > + status = "okay"; > + }; > +}; > + > + > +&iomuxc { > + > + pinctrl_secure: securegrp { Unused? > + fsl,pins = < > + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1 > + >; > + }; > + > + pinctrl_uart1: uart1grp { > + fsl,pins = < > + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 > + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 > + >; > + }; > + > + pinctrl_uart2: uart2grp { > + fsl,pins = < > + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 > + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 > + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 > + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 > + >; > + }; > + > + pinctrl_uart3: uart3grp { > + fsl,pins = < > + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 > + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 > + >; > + }; > + > + pinctrl_uart4: uart4grp { > + fsl,pins = < > + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 > + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 > + >; > + }; > + > + pinctrl_uart5: uart5grp { > + fsl,pins = < > + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 > + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 > + >; > + }; > + > + pinctrl_emcon_gpio1: emcongpio1 { > + fsl,pins = < > + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x0b0b1 > + >; > + }; Try to keep these pinctrl entries alphabetically sorted. > + > + pinctrl_emcon_gpio2: emcongpio2 { > + fsl,pins = < > + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0b0b1 > + >; > + }; > + > + pinctrl_emcon_gpio3: emcongpio3 { > + fsl,pins = < > + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0b0b1 > + >; > + }; > + > + pinctrl_emcon_gpio4: emcongpio4 { > + fsl,pins = < > + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0b0b1 > + >; > + }; > + > + pinctrl_emcon_gpio5: emcongpio5 { > + fsl,pins = < > + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x0b0b1 > + >; > + }; > + > + pinctrl_emcon_gpio6: emcongpio6 { > + fsl,pins = < > + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0b0b1 > + >; > + }; > + > + pinctrl_emcon_gpio7: emcongpio7 { > + fsl,pins = < > + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0b0b1 > + >; > + }; > + > + pinctrl_emcon_gpio8: emcongpio8 { > + fsl,pins = < > + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0b0b1 > + >; > + }; > + > + pinctrl_emcon_irq_a: emconirqa { > + fsl,pins = < > + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x0b0b1 > + >; > + }; > + > + pinctrl_emcon_irq_b: emconirqb { > + fsl,pins = < > + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x0b0b1 > + >; > + }; > + > + pinctrl_emcon_irq_c: emconirqc { > + fsl,pins = < > + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0b0b1 > + >; > + }; > + > + pinctrl_emcon_wake: emconwake { > + fsl,pins = < > + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 > + >; > + }; > + > + pinctrl_emcon_irq_pwr: emconirqpwr { > + fsl,pins = < > + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0b0b1 > + >; > + }; > + > + pinctrl_som_leds: somledgrp { > + fsl,pins = < > + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x0b0b1 > + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x0b0b1 > + >; > + }; > + > + pinctrl_nor_flash: norflashgrp { > + fsl,pins = < > + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b1 > + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 > + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 > + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 > + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 > + >; > + }; > + > + pinctrl_ecspi2: ecspi2grp { > + fsl,pins = < > + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 > + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 > + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 > + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1 > + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 > + >; > + }; > + > + pinctrl_pwm_fan: pwmfan { > + fsl,pins = < > + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x0b0b1 > + >; > + }; > + > + pinctrl_can1: can1grp { > + fsl,pins = < > + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 > + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 > + >; > + }; > + > + pinctrl_can2: can2grp { > + fsl,pins = < > + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1 > + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1 > + >; > + }; > + > + pinctrl_spdif_out: spdifout { > + fsl,pins = < > + MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091 > + >; > + }; > + > + pinctrl_spdif_in: spdifin { > + fsl,pins = < > + MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 > + >; > + }; > + > + pinctrl_cpi1: csi0grp { > + fsl,pins = < > + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1 > + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b1 > + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b1 > + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b1 > + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b1 > + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b1 > + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b1 > + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b1 > + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b1 > + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b1 > + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b1 > + >; > + }; > + > + /*camera2-pinctrl is in imx6q-emcon.dtsi or imx6dl-emcon.dtsi*/ > + > + pinctrl_pcie_ctrl: pciegrp { > + fsl,pins = < > + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1 > + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 > + >; > + }; > + > + pinctrl_audmux: audmux { > + fsl,pins = < > + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 > + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b060 > + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130B0 > + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b060 > + >; > + }; > + > + pinctrl_i2c1: i2c1grp { > + fsl,pins = < > + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 > + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 > + >; > + }; > + > + pinctrl_i2c2: i2c2grp { > + fsl,pins = < > + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 > + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 > + >; > + }; > + > + pinctrl_i2c3: i2c3grp { > + fsl,pins = < > + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4000b070 > + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b870 > + >; > + }; > + > + pinctrl_pmic: pmicgrp { > + fsl,pins = < > + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0b0b1 > + >; > + }; > + > + pinctrl_usb_host1: usbhgrp { > + fsl,pins = < > + MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x1B058 > + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1B058 > + >; > + }; > + > + pinctrl_usb_otg: usbotggrp { > + fsl,pins = < > + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 > + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x17059 > + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x17059 > + >; > + }; > + > + pinctrl_lvds_reg: lvdsreggrp { > + fsl,pins = < > + MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x0b0b1 > + >; > + }; > + > + pinctrl_lvds_bl: lvdsbacklightgrp { > + fsl,pins = < > + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x0b0b1 > + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b1 > + >; > + }; > + > + pinctrl_irq_touch1: irqtouch1 { > + fsl,pins = < > + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x0b0b1 > + >; > + }; > + > + pinctrl_rgb_bl_en: rgbenable { > + fsl,pins = < > + MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x0b0b1 > + >; > + }; > + > + pinctrl_irq_touch2: irqtouch2 { > + fsl,pins = < > + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x0b0b1 > + >; > + }; > + > + pinctrl_rgb_bl: rgbbacklightgrp { > + fsl,pins = < > + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x0b0b1 > + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b1 > + >; > + }; > + > + pinctrl_rgb24_display: rgbgrp { > + fsl,pins = < > + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 > + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 > + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 > + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 > + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 > + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 > + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 > + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 > + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 > + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 > + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 > + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 > + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 > + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 > + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 > + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 > + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 > + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 > + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 > + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 > + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 > + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 > + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 > + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 > + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 > + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 > + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 > + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 > + >; > + }; > + > + pinctrl_enet: enetgrp { > + fsl,pins = < > + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b030 > + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b030 > + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 > + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 > + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 > + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 > + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 > + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 > + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001a0b1 > + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 > + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 > + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 > + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 > + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 > + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 > + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b058 > + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 > + >; > + }; > + > + > + pinctrl_usdhc3: usdhc3grp { > + fsl,pins = < > + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 > + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 > + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 > + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 > + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 > + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 > + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 > + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 > + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 > + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 > + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 > + >; > + }; > + > + pinctrl_usdhc1: usdhc1grp { > + fsl,pins = < > + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 > + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 > + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 > + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 > + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 > + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 > + MX6QDL_PAD_GPIO_1__SD1_CD_B 0x1b0b1 > + MX6QDL_PAD_DI0_PIN4__SD1_WP 0x1b0b1 > + >; > + }; > + > + pinctrl_usdhc2: usdhc2grp { > + fsl,pins = < > + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 > + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 > + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 > + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 > + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 > + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 > + MX6QDL_PAD_GPIO_4__SD2_CD_B 0x1b0b1 > + MX6QDL_PAD_GPIO_2__SD2_WP 0x1b0b1 > + >; > + }; > + > +}; > + > + > +&i2c1 { > + clock-frequency = <100000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c1>; > + status = "okay"; > + > + rtc: rtc at 68 { > + compatible = "dallas,ds1307"; > + reg = <0x68>; > + }; > + > + da9063: pmic at 58 { > + compatible = "dlg,da9063"; > + reg = <0x58>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pmic>; > + interrupt-parent = <&gpio2>; > + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; > + interrupt-controller; > + > + onkey { > + compatible = "dlg,da9063-onkey"; > + wakeup-source; > + }; > + > + wdt { s/wdt/watchdog > + compatible = "dlg,da9063-watchdog"; > + timeout-sec = <0>; > + }; > + > + regulators { > + vddcore_reg: bcore1 { > + regulator-min-microvolt = <1100000>; > + regulator-max-microvolt = <1450000>; > + regulator-ramp-delay = <20000>; > + regulator-name = "DA9063_CORE"; > + regulator-always-on; > + }; > + > + vddsoc_reg: bcore2 { > + regulator-min-microvolt = <1100000>; > + regulator-max-microvolt = <1450000>; > + regulator-ramp-delay = <20000>; > + regulator-name = "DA9063_SOC"; > + regulator-always-on; > + }; > + > + vdd_ddr3_reg: bpro { > + regulator-min-microvolt = <1500000>; > + regulator-max-microvolt = <1500000>; > + regulator-ramp-delay = <20000>; > + regulator-always-on; > + }; > + > + vdd_3v3_reg: bperi { > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-ramp-delay = <20000>; > + regulator-always-on; > + }; > + > + vdd_sata_reg: ldo3 { > + regulator-min-microvolt = <2500000>; > + regulator-max-microvolt = <2500000>; > + regulator-always-on; > + }; > + vdd_mipi_reg: ldo4 { > + regulator-min-microvolt = <2500000>; > + regulator-max-microvolt = <2500000>; > + regulator-always-on; > + }; > + > + vdd_mx6_snvs_reg: ldo5 { > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-always-on; > + }; > + > + vdd_hdmi_reg: ldo6 { > + regulator-min-microvolt = <2500000>; > + regulator-max-microvolt = <2500000>; > + regulator-always-on; > + regulator-boot-on; > + }; > + > + vdd_pcie_reg: ldo7 { > + regulator-min-microvolt = <2500000>; > + regulator-max-microvolt = <2500000>; > + regulator-always-on; > + }; > + > + vdd_1V8_reg: ldo8 { > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + regulator-always-on; > + }; > + > + vdd_3V3_sdc_reg: ldo9 { > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <3300000>; > + regulator-always-on; > + }; > + > + vdd_1V2_reg: ldo10 { > + regulator-min-microvolt = <1200000>; > + regulator-max-microvolt = <1200000>; > + regulator-always-on; > + }; > + }; > + }; > +}; > + > +&uart1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart1>; > + status = "okay"; > +}; > + > +&uart2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart2>; > +}; > + > +&uart3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart3>; > +}; > + > +&uart4 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart4>; > +}; > + > +&uart5 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart5>; > +}; > + > +&fec { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_enet>; > + phy-mode = "rgmii"; > + phy-reset-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; > + phy-reset-duration = <50>; > + phy-supply = <&vdd_1V8_reg>; > + phy-handle = <&ksz9031>; > + status = "okay"; > + > + > + mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + > + ksz9031: phy at 0 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <0>; > + interrupt-parent = <&gpio1>; > + interrupts = <30 IRQ_TYPE_EDGE_FALLING>; > + rxdv-skew-ps = <480>; > + txen-skew-ps = <480>; > + rxd0-skew-ps = <480>; > + rxd1-skew-ps = <480>; > + rxd2-skew-ps = <480>; > + rxd3-skew-ps = <480>; > + txd0-skew-ps = <420>; > + txd1-skew-ps = <420>; > + txd2-skew-ps = <360>; > + txd3-skew-ps = <360>; > + txc-skew-ps = <1020>; > + rxc-skew-ps = <960>; > + }; > + }; > +}; > + > + > +&usdhc3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usdhc3>; > + non-removable; > + bus-width = <8>; > + status = "okay"; > +}; > + > +&pcie { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pcie_ctrl>; > + reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; > + disable-gpio = <&gpio2 22 GPIO_ACTIVE_LOW>; > +}; > + > +&i2c2 { > + clock-frequency = <100000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c2>; > +}; > + > +&usdhc1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usdhc1>; > + fsl,wp-controller; > +}; > + > +&usdhc2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usdhc2>; > + fsl,wp-controller; > +}; > + > + > +&ipu1_di0_disp0 { > + remote-endpoint = <&rgb_encoder_in>; > +}; > + > +&pwm1 { > + status = "okay"; > +}; > + > +&pwm3 { > + status = "okay"; > +}; > + > +&pwm4 { > + status = "okay"; > +}; > + > +&ecspi2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_ecspi2>; > + cs-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>, > + <&gpio2 26 GPIO_ACTIVE_HIGH>; > +}; > + > +&ecspi4 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_nor_flash>; > +}; > + > +&can1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_can1>; > +}; > + > +&can2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_can2>; > +}; > + > +&usbh1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usb_host1>; > +}; > + > +&usbotg { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usb_otg>; > + vbus-supply = <®_usb_otg>; > + dr_mode = "peripheral"; > +}; > + > +/******device power Management*********/ > + > +&cpu0 { > + voltage-tolerance = <2>; > +}; > + > +®_arm { > + vin-supply = <&vddcore_reg>; > +}; > + > +®_soc { > + vin-supply = <&vddsoc_reg>; > +}; > + > +®_pu { > + vin-supply = <&vddsoc_reg>; > +}; > + > + > + > +/*******Disabled HW following***********/ > + > + > +&weim { > + status = "disabled"; > +}; Isn't weim disabled by default? Shawn > + > +&snvs_rtc { > + status = "disabled"; > +}; > -- > 2.11.0 > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Shawn Guo Subject: Re: [PATCH v3 5/6] ARM: dts: Add support for emtrion emCON-MX6 series Date: Mon, 23 Apr 2018 16:44:56 +0800 Message-ID: <20180423084454.GZ25429@dragon> References: <20171220134710.64479-2-jan.tuerk@emtrion.com> <20180420125108.14197-1-jan.tuerk@emtrion.com> <20180420125108.14197-6-jan.tuerk@emtrion.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <20180420125108.14197-6-jan.tuerk@emtrion.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: jan.tuerk@emtrion.com Cc: Mark Rutland , devicetree@vger.kernel.org, David Airlie , Russell King , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Rob Herring , Thierry Reding , Sascha Hauer , Fabio Estevam , linux-arm-kernel@lists.infradead.org List-Id: devicetree@vger.kernel.org T24gRnJpLCBBcHIgMjAsIDIwMTggYXQgMDI6NTA6NTJQTSArMDIwMCwgamFuLnR1ZXJrQGVtdHJp b24uY29tIHdyb3RlOgo+IEZyb206IEphbiBUdWVyayA8amFuLnR1ZXJrQGVtdHJpb24uY29tPgo+ IAo+IFRoaXMgcGF0Y2ggYWRkcyBzdXBwb3J0IGZvciB0aGUgZW10cmlvbiBHbWJIIGVtQ09OLU1Y NiBtb2R1bGVzLgo+IFRoZXkgYXJlIGF2YWlsYWJsZSB3aXRoIGlteC42IFNvbG8sIER1YWwtTGl0 ZSwgRHVhbCBhbmQgUXVhZAo+IGVxdWlwcGVkIHdpdGggTWVtb3J5IGZyb20gNTEyTUIgdG8gMkdC IChjb25maWd1cmVkIGJ5IFUtQm9vdCkuCj4gCj4gT3VyIGRlZmF1bHQgZGV2ZWxvcGVyLUtpdCBz aGlwcyB3aXRoIHRoZSBBdmFyaSBiYXNlYm9hcmQgYW5kIHRoZQo+IEVEVCBFVE0wNzAwRzBCREg2 IERpc3BsYXkgKGlteDZbcXxkbF0tZW1jb24tYXZhcmkpLgo+IAo+IFRoZSBkZXZpY2V0cmVlIGlz IHNwbGl0IGludG8gdGhlIGNvbW1vbiBwYXJ0IHByb3ZpZGluZyBhbGwgbW9kdWxlCj4gY29tcG9u ZW50cyBhbmQgdGhlIGJhc2ljIHN1cHBvcnQgZm9yIGFsbCBTb0MgdmVyc2lvbnMKPiAoaW14NnFk bC1lbWNvbi5kdHNpKSBhbmQgcGFydHMgd2hpY2ggYXJlIGkubXg2IFN8REwgYW5kIER8USByZWxl dmFudC4KPiBGaW5hbGx5IHRoZSBzdXBwb3J0IGZvciB0aGUgYXZhcmkgYmFzZWJvYXJkIGluIHRo ZSBkZXZlbG9wZXIta2l0Cj4gY29uZmlndXJhdGlvbiBpcyBwcm92aWRlZCBieSB0aGUgZW1jb24t YXZhcmkgZHRzIGZpbGVzLgo+IAo+IFNpZ25lZC1vZmYtYnk6IEphbiBUdWVyayA8amFuLnR1ZXJr QGVtdHJpb24uY29tPgo+IC0tLQo+ICBEb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3Mv YXJtL2VtdHJpb24udHh0IHwgIDEzICsKCkl0J3MgYmV0dGVyIHRvIGhhdmUgYSBzZXBhcmF0ZSBw YXRjaCBmb3IgYmluZGluZ3MgZG9jLCB3aGljaCBuZWVkcyB0byBiZQphY2tub3dsZWRnZWQgYnkg RFQgbWFpbnRhaW5lcnMuCgo+ICBhcmNoL2FybS9ib290L2R0cy9NYWtlZmlsZSAgICAgICAgICAg ICAgICAgICAgICAgIHwgICAyICsKPiAgYXJjaC9hcm0vYm9vdC9kdHMvaW14NmRsLWVtY29uLWF2 YXJpLmR0cyAgICAgICAgICB8IDIyNCArKysrKysKPiAgYXJjaC9hcm0vYm9vdC9kdHMvaW14NmRs LWVtY29uLmR0c2kgICAgICAgICAgICAgICB8ICAyNyArCj4gIGFyY2gvYXJtL2Jvb3QvZHRzL2lt eDZxLWVtY29uLWF2YXJpLmR0cyAgICAgICAgICAgfCAyMjQgKysrKysrCj4gIGFyY2gvYXJtL2Jv b3QvZHRzL2lteDZxLWVtY29uLmR0c2kgICAgICAgICAgICAgICAgfCAgMjcgKwo+ICBhcmNoL2Fy bS9ib290L2R0cy9pbXg2cWRsLWVtY29uLmR0c2kgICAgICAgICAgICAgIHwgODM4ICsrKysrKysr KysrKysrKysrKysrKysKPiAgNyBmaWxlcyBjaGFuZ2VkLCAxMzU1IGluc2VydGlvbnMoKykKPiAg Y3JlYXRlIG1vZGUgMTAwNjQ0IERvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9hcm0v ZW10cmlvbi50eHQKPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGFyY2gvYXJtL2Jvb3QvZHRzL2lteDZk bC1lbWNvbi1hdmFyaS5kdHMKPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGFyY2gvYXJtL2Jvb3QvZHRz L2lteDZkbC1lbWNvbi5kdHNpCj4gIGNyZWF0ZSBtb2RlIDEwMDY0NCBhcmNoL2FybS9ib290L2R0 cy9pbXg2cS1lbWNvbi1hdmFyaS5kdHMKPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGFyY2gvYXJtL2Jv b3QvZHRzL2lteDZxLWVtY29uLmR0c2kKPiAgY3JlYXRlIG1vZGUgMTAwNjQ0IGFyY2gvYXJtL2Jv b3QvZHRzL2lteDZxZGwtZW1jb24uZHRzaQo+IAo+IGRpZmYgLS1naXQgYS9Eb2N1bWVudGF0aW9u L2RldmljZXRyZWUvYmluZGluZ3MvYXJtL2VtdHJpb24udHh0IGIvRG9jdW1lbnRhdGlvbi9kZXZp Y2V0cmVlL2JpbmRpbmdzL2FybS9lbXRyaW9uLnR4dAo+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0Cj4g aW5kZXggMDAwMDAwMDAwMDAwLi4zZmY2YzZjMjAzNGQKPiAtLS0gL2Rldi9udWxsCj4gKysrIGIv RG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL2FybS9lbXRyaW9uLnR4dAo+IEBAIC0w LDAgKzEsMTMgQEAKPiArRW10cmlvbiBEZXZpY2V0cmVlIEJpbmRpbmdzCj4gKz09PT09PT09PT09 PT09PT09PT09PT09PT09PQo+ICsKPiArZW1DT04gU2VyaWVzOgo+ICstLS0tLS0tLS0tLS0tCj4g Kwo+ICtSZXF1aXJlZCByb290IG5vZGUgcHJvcGVydGllcwo+ICsJLSBjb21wYXRpYmxlOgo+ICsJ LSAiZW10cmlvbixlbWNvbi1teDYiLCAiZnNsLGlteDZxIiwgImZzbCxpbXg2ZGwiOyA6IGVtQ09O LU1YNiBHZW5lcmljIFNvTQo+ICsJLSAiZW10cmlvbixlbWNvbi1teDYiLCAiZnNsLGlteDZxIjsg CQk6IGVtQ09OLU1YNkQgb3IgZW1DT04tTVg2USBTb00KPiArCS0gImVtdHJpb24sZW1jb24tbXg2 LWF2YXJpIiwgImZzbCxpbXg2cSI7CTogZW1DT04tTVg2RCBvciBlbUNPTi1NWDZRIFNvTSBvbiBB dmFyaSBCYXNlCj4gKwktICJlbXRyaW9uLGVtY29uLW14NiIsICJmc2wsaW14NmRsIjsgCQk6IGVt Q09OLU1YNlMgb3IgZW1DT04tTVg2REwgU29NCj4gKwktICJlbXRyaW9uLGVtY29uLW14Ni1hdmFy aSIsICJmc2wsaW14NmRsIjsJOiBlbUNPTi1NWDZTIG9yIGVtQ09OLU1YNkRMIFNvTSBvbiBBdmFy aSBCYXNlCj4gZGlmZiAtLWdpdCBhL2FyY2gvYXJtL2Jvb3QvZHRzL01ha2VmaWxlIGIvYXJjaC9h cm0vYm9vdC9kdHMvTWFrZWZpbGUKPiBpbmRleCA3ZTI0MjQ5NTc4MDkuLjA1YjkzMGRhM2ZkYSAx MDA2NDQKPiAtLS0gYS9hcmNoL2FybS9ib290L2R0cy9NYWtlZmlsZQo+ICsrKyBiL2FyY2gvYXJt L2Jvb3QvZHRzL01ha2VmaWxlCj4gQEAgLTM4MSw2ICszODEsNyBAQCBkdGItJChDT05GSUdfU09D X0lNWDZRKSArPSBcCj4gIAlpbXg2ZGwtY3Vib3gtaS1lbW1jLXNvbS12MTUuZHRiIFwKPiAgCWlt eDZkbC1jdWJveC1pLXNvbS12MTUuZHRiIFwKPiAgCWlteDZkbC1kZmktZnM3MDAtbTYwLmR0YiBc Cj4gKwlpbXg2ZGwtZW1jb24tYXZhcmkuZHRiIFwKPiAgCWlteDZkbC1ndzUxeHguZHRiIFwKPiAg CWlteDZkbC1ndzUyeHguZHRiIFwKPiAgCWlteDZkbC1ndzUzeHguZHRiIFwKPiBAQCAtNDQyLDYg KzQ0Myw3IEBAIGR0Yi0kKENPTkZJR19TT0NfSU1YNlEpICs9IFwKPiAgCWlteDZxLWRpc3BsYXk1 LXRpYW5tYS10bTA3MC0xMjgweDc2OC5kdGIgXAo+ICAJaW14NnEtZG1vLWVkbXFteDYuZHRiIFwK PiAgCWlteDZxLWRtcy1iYTE2LmR0YiBcCj4gKwlpbXg2cS1lbWNvbi1hdmFyaS5kdGIgXAo+ICAJ aW14NnEtZXZpLmR0YiBcCj4gIAlpbXg2cS1nazgwMi5kdGIgXAo+ICAJaW14NnEtZ3c1MXh4LmR0 YiBcCj4gZGlmZiAtLWdpdCBhL2FyY2gvYXJtL2Jvb3QvZHRzL2lteDZkbC1lbWNvbi1hdmFyaS5k dHMgYi9hcmNoL2FybS9ib290L2R0cy9pbXg2ZGwtZW1jb24tYXZhcmkuZHRzCj4gbmV3IGZpbGUg bW9kZSAxMDA2NDQKPiBpbmRleCAwMDAwMDAwMDAwMDAuLjIzNDRmYjk0OThlMwo+IC0tLSAvZGV2 L251bGwKPiArKysgYi9hcmNoL2FybS9ib290L2R0cy9pbXg2ZGwtZW1jb24tYXZhcmkuZHRzCj4g QEAgLTAsMCArMSwyMjQgQEAKPiArLy8gU1BEWC1MaWNlbnNlLUlkZW50aWZpZXI6IChHUEwtMi4w IG9yIE1JVCkKPiArLyogQ29weXJpZ2h0IChDKSAyMDE4IGVtdHJpb24gR21iSAo+ICsgKiBBdXRo b3I6IEphbiBUdWVyayAgPGphbi50dWVya0BlbXRyaW9uLmNvbT4KPiArICovCgovKgogKiBDb3B5 cmlnaHQgLi4uCiAqLwoKPiArCj4gKy9kdHMtdjEvOwo+ICsjaW5jbHVkZSAiaW14NmRsLmR0c2ki Cj4gKyNpbmNsdWRlICJpbXg2cWRsLWVtY29uLmR0c2kiCj4gKyNpbmNsdWRlICJpbXg2ZGwtZW1j b24uZHRzaSIgLypJbmNsdWRlIGNhbWVyYTIgcGlubXV4Ki8KCi8qIGJsYSBibGEgKi8KCj4gKwo+ ICsvIHsKPiArCW1vZGVsID0gImVtdHJpb24gU29NIGVtQ09OLU1YNiBTb2xvL0R1YWwtTGl0ZSBB dmFyaSI7Cj4gKwljb21wYXRpYmxlID0gImVtdHJpb24sZW1jb24tbXg2LWF2YXJpIiwgImZzbCxp bXg2ZGwiOwo+ICsKPiArCWFsaWFzZXMgewo+ICsJCW1tYzAgPSAmdXNkaGMzOwo+ICsJCW1tYzIg PSAmdXNkaGMxOwo+ICsJCW1tYzEgPSAmdXNkaGMyOwo+ICsJCW1tYzMgPSAmdXNkaGM0Owo+ICsJ fTsKPiArCj4gKwljaG9zZW4gewo+ICsJCXN0ZG91dC1wYXRoID0gPCZ1YXJ0MT47Cj4gKwl9Owo+ ICsKPiArCW1lbW9yeSB7CgpUaGUgdW5pdC1hZGRyZXNzIGlzIG1pc3NpbmcuCgo+ICsJCXJlZyA9 IDwweDEwMDAwMDAwIDB4NDAwMDAwMDA+Owo+ICsJfTsKPiArCj4gKwlzdXBwbGllcyB7Cj4gKwkJ Y29tcGF0aWJsZSA9ICJzaW1wbGUtYnVzIjsKPiArCQkjYWRkcmVzcy1jZWxscyA9IDwxPjsKPiAr CQkjc2l6ZS1jZWxscyA9IDwwPjsKCkRUIG1haW50YWluZXJzIGRvIG5vdCBsaWtlIHRoaXMgZmFr ZSBjb250YWluZXIgbm9kZS4gIFBsZWFzZSBwdXQgdGhlCmZpeGVkIHJlZ3VsYXRvciBub2RlcyBk aXJlY3RseSB1bmRlciByb290IHdpdGggYSB1bmlxdWUgbmFtZSBsaWtlIGJlbG93LgoKCXJlZ194 eHg6IHJlZ3VsYXRvci14eHggewoJCS4uLgoJfTsKCj4gKwo+ICsJCXdhbGxwbHVnNXAwOiBzdXBw bHlAMCB7Cj4gKwkJCWNvbXBhdGlibGUgPSAicmVndWxhdG9yLWZpeGVkIjsKPiArCQkJcmVnID0g PDA+Owo+ICsJCQlyZWd1bGF0b3ItbmFtZSA9ICJXQUxMLVBMVUciOwo+ICsJCQlyZWd1bGF0b3It bWluLW1pY3Jvdm9sdCA9IDw1MDAwMDAwPjsKPiArCQkJcmVndWxhdG9yLW1heC1taWNyb3ZvbHQg PSA8NTAwMDAwMD47Cj4gKwkJCXJlZ3VsYXRvci1hbHdheXMtb247Cj4gKwkJCXJlZ3VsYXRvci1i b290LW9uOwo+ICsJCX07Cj4gKwo+ICsJCWJhc2UzcDM6IHN1cHBseUAxIHsKPiArCQkJY29tcGF0 aWJsZSA9ICJyZWd1bGF0b3ItZml4ZWQiOwo+ICsJCQlyZWcgPSA8MT47Cj4gKwkJCXZpbi1zdXBw bHkgPSA8JndhbGxwbHVnNXAwPjsKPiArCQkJcmVndWxhdG9yLW5hbWUgPSAiM1YzLWF2YXJpIjsK PiArCQkJcmVndWxhdG9yLW1pbi1taWNyb3ZvbHQgPSA8MzMwMDAwMD47Cj4gKwkJCXJlZ3VsYXRv ci1tYXgtbWljcm92b2x0ID0gPDMzMDAwMDA+Owo+ICsJCQlyZWd1bGF0b3ItYWx3YXlzLW9uOwo+ ICsJCQlyZWd1bGF0b3ItYm9vdC1vbjsKPiArCQl9Owo+ICsKPiArCQliYXNlMXA1OiBzdXBwbHlA MiB7Cj4gKwkJCWNvbXBhdGlibGUgPSAicmVndWxhdG9yLWZpeGVkIjsKPiArCQkJcmVnID0gPDI+ Owo+ICsJCQl2aW4tc3VwcGx5ID0gPCZiYXNlM3AzPjsKPiArCQkJcmVndWxhdG9yLW5hbWUgPSAi MVY1LWF2YXJpIjsKPiArCQkJcmVndWxhdG9yLW1pbi1taWNyb3ZvbHQgPSA8MTUwMDAwMD47Cj4g KwkJCXJlZ3VsYXRvci1tYXgtbWljcm92b2x0ID0gPDE1MDAwMDA+Owo+ICsJCQlyZWd1bGF0b3It YWx3YXlzLW9uOwo+ICsJCQlyZWd1bGF0b3ItYm9vdC1vbjsKPiArCQl9Owo+ICsKPiArCQlyZWdf dXNiX290Zzogb3RndmJ1c0AzIHsKPiArCQkJY29tcGF0aWJsZSA9ICJyZWd1bGF0b3ItZml4ZWQi Owo+ICsJCQlyZWcgPSA8Mz47Cj4gKwkJCXZpbi1zdXBwbHkgPSA8JndhbGxwbHVnNXAwPjsKPiAr CQkJcmVndWxhdG9yLW5hbWUgPSAiT1RHX1ZCVVMiOwo+ICsJCQlyZWd1bGF0b3ItbWluLW1pY3Jv dm9sdCA9IDw1MDAwMDAwPjsKPiArCQkJcmVndWxhdG9yLW1heC1taWNyb3ZvbHQgPSA8NTAwMDAw MD47Cj4gKwkJCWdwaW8gPSA8JmdwaW8xIDggR1BJT19BQ1RJVkVfTE9XPjsKPiArCQkJcmVndWxh dG9yLWFsd2F5cy1vbjsKPiArCQl9Owo+ICsKPiArCX07Cj4gKwo+ICsKPiArCXNuZG9zYzogMTJN SFpvc2MgewoKCWNsb2NrLXh4eCB7CgkJLi4uCgl9OwoKPiArCQljb21wYXRpYmxlID0gImZpeGVk LWNsb2NrIjsKPiArCQkjY2xvY2stY2VsbHMgPSA8MD47Cj4gKwkJY2xvY2stZnJlcXVlbmN5ICA9 IDwxMjAwMDAwMD47Cj4gKwl9Owo+ICsKPiArCXNvdW5kIHsKPiArCQljb21wYXRpYmxlID0gImZz bCxpbXgtYXVkaW8tc2d0bDUwMDAiOwo+ICsJCW1vZGVsID0gImVtQ09OLWF2YXJpLXNndGw1MDAw IjsKPiArCQlzc2ktY29udHJvbGxlciA9IDwmc3NpMj47Cj4gKwkJYXVkaW8tY29kZWMgPSA8JnNn dGw1MDAwPjsKPiArCQlhdWRpby1yb3V0aW5nID0KPiArCQkJIkhlYWRwaG9uZSBKYWNrIiwgIkhQ X09VVCI7Cj4gKwkJbXV4LWludC1wb3J0ID0gPDI+Owo+ICsJCW11eC1leHQtcG9ydCA9IDwzPjsK PiArCX07Cj4gKwo+ICt9Owo+ICsKPiArCgpPbmUgbmV3bGluZSBpcyBnb29kIGVub3VnaC4KCj4g KyZpb211eGMgewo+ICsJcGluY3RybC1uYW1lcyA9ICJkZWZhdWx0IjsKPiArCS8qVW51c2VkIGVt Q09OLU1YNiBvdXRwdXRzIG9uIEFWQVJJKi8KPiArCXBpbmN0cmwtMCA9IDwKPiArCQkJCSAmcGlu Y3RybF9lbWNvbl9ncGlvMSAmcGluY3RybF9lbWNvbl9ncGlvMgo+ICsJCQkJICZwaW5jdHJsX2Vt Y29uX2dwaW8zICZwaW5jdHJsX2VtY29uX2dwaW81Cj4gKwkJCQkgJnBpbmN0cmxfZW1jb25fZ3Bp bzYgJnBpbmN0cmxfZW1jb25fZ3BpbzcKPiArCQkJCSAmcGluY3RybF9lbWNvbl9ncGlvOCAmcGlu Y3RybF9lbWNvbl9pcnFfYQo+ICsJCQkJICZwaW5jdHJsX2VtY29uX2lycV9iICZwaW5jdHJsX2Vt Y29uX2lycV9jCj4gKwkJCQkgJnBpbmN0cmxfZW1jb25faXJxX3B3ciAmcGluY3RybF9ub3JfZmxh c2gKPiArCQkJCSAmcGluY3RybF91c2RoYzIKPiArCQkJCSAmcGluY3RybF9zcGRpZl9vdXQgICAg ICZwaW5jdHJsX3NwZGlmX2luCj4gKwkJCQkgJnBpbmN0cmxfY3BpMSAgICAgICAgICAmcGluY3Ry bF9jcGkyCj4gKwkJCQk+OwoKT25seSBwaW5zIHdpdGhvdXQgY2xlYXIgY29uc3VtZXIgc2hvdWxk IGJlIHB1dCBpbnRvIGhvZyBncm91cC4gIEFsc28gdGhlCmluZGVudCBzZWVtcyBicm9rZW4uCgo+ ICt9Owo+ICsKPiArJmF1ZG11eCB7Cj4gKwlwaW5jdHJsLW5hbWVzID0gImRlZmF1bHQiOwo+ICsJ cGluY3RybC0wID0gPCZwaW5jdHJsX2F1ZG11eD47Cj4gKwlzdGF0dXMgPSAib2theSI7Cj4gK307 Cj4gKwo+ICsKPiArCgpPbmUgbmV3bGluZSBpcyBnb29kIGVub3VnaC4gIEFsc28sIHBsZWFzZSB0 cnkgdG8gc29ydCB0aGVzZSBsYWJlbGxlZApub2RlcyBhbHBoYWJldGljYWxseS4KCj4gKyZpMmMz IHsKPiArCWNsb2NrLWZyZXF1ZW5jeSA9IDwxMDAwMDA+Owo+ICsJcGluY3RybC1uYW1lcyA9ICJk ZWZhdWx0IjsKPiArCXBpbmN0cmwtMCA9IDwmcGluY3RybF9pMmMzPjsKPiArCXN0YXR1cyA9ICJv a2F5IjsKPiArCj4gKwlzZ3RsNTAwMDogYXVkaW8tY29kZWNAYSB7Cj4gKwkJY29tcGF0aWJsZSA9 ICJmc2wsc2d0bDUwMDAiOwo+ICsJCXJlZyA9IDwweDBhPjsKPiArCQljbG9ja3MgPSA8JnNuZG9z Yz47Cj4gKwkJVkREQS1zdXBwbHkgPSA8JmJhc2UzcDM+Owo+ICsJCVZERElPLXN1cHBseSA9IDwm YmFzZTNwMz47Cgojc291bmQtZGFpLWNlbGxzIGlzIG1pc3NpbmcuCgo+ICsJfTsKPiArCj4gKwli b2FyZElEOiBwY2E4NzU0YUAzYSB7CgpQbGVhc2UgZmluZCBhIG1vcmUgZ2VuZXJpYyBub2RlIG5h bWUgZm9yIGl0LgoKPiArCQljb21wYXRpYmxlID0gIm54cCxwY2E4NTc0IjsKPiArCQlyZWcgPSA8 MHgzYT47Cj4gKwkJZ3Bpby1jb250cm9sbGVyOwo+ICsJCSNncGlvLWNlbGxzID0gPDE+Owo+ICsJ fTsKPiArCj4gKwljYXB0b3VjaDogdG91Y2hzY3JlZW5AMzggewo+ICsJCWNvbXBhdGlibGUgPSAi ZWR0LGVkdC1mdDU0MDYiOwo+ICsJCXJlZyA9IDwweDM4PjsKPiArCQlwaW5jdHJsLW5hbWVzID0g ImRlZmF1bHQiOwo+ICsJCXBpbmN0cmwtMCA9IDwmcGluY3RybF9pcnFfdG91Y2gyICZwaW5jdHJs X2VtY29uX2dwaW80PjsKPiArCQlpbnRlcnJ1cHQtcGFyZW50ID0gPCZncGlvNj47Cj4gKwkJaW50 ZXJydXB0cyA9IDwzMSBJUlFfVFlQRV9FREdFX0ZBTExJTkc+Owo+ICsJCXdha2UtZ3Bpb3MgPSA8 JmdwaW8yIDMgR1BJT19BQ1RJVkVfSElHSD47Cj4gKwkJd2FrZXVwLXNvdXJjZTsKPiArCQlzdGF0 dXMgPSAib2theSI7CgpUaGUgIm9rYXkiIHN0YXR1cyBpcyBvbmx5IG5lZWRlZCB0byBmbGlwIHRo ZSBkZWZhdWx0ICJkaXNhYmxlZCIgZGV2aWNlLgoKPiArCX07Cj4gK307Cj4gKwo+ICsmc3NpMiB7 Cj4gKwlzdGF0dXMgPSAib2theSI7Cj4gK307Cj4gKwo+ICsmcmdiX2VuY29kZXIgewo+ICsJc3Rh dHVzID0gIm9rYXkiOwo+ICt9Owo+ICsKPiArJnJnYl9wYW5lbCB7Cj4gKwljb21wYXRpYmxlID0g ImVkdCxldG0wNzAwZzBiZGg2IjsKPiArCXN0YXR1cyA9ICJva2F5IjsKPiArfTsKPiArCj4gKyZp MmMyIHsKPiArCXN0YXR1cyA9ICJva2F5IjsKPiArfTsKPiArCj4gKyZoZG1pIHsKPiArCWRkYy1p MmMtYnVzID0gPCZpMmMyPjsKPiArCXN0YXR1cyA9ICJva2F5IjsKPiArfTsKPiArCj4gKyZ1c2Jo MSB7Cj4gKwlzdGF0dXMgPSAib2theSI7Cj4gK307Cj4gKwo+ICsmdXNib3RnIHsKPiArCXN0YXR1 cyA9ICJva2F5IjsKPiArfTsKPiArCj4gKyZwY2llIHsKPiArCXN0YXR1cyA9ICJva2F5IjsKPiAr fTsKPiArCj4gKyZ1c2RoYzEgewo+ICsJc3RhdHVzID0gIm9rYXkiOwo+ICt9Owo+ICsKPiArJmNh bjEgewo+ICsJc3RhdHVzID0gIm9rYXkiOwo+ICt9Owo+ICsKPiArJmNhbjIgewo+ICsJc3RhdHVz ID0gIm9rYXkiOwo+ICt9Owo+ICsKPiArJnVhcnQyIHsKPiArCXN0YXR1cyA9ICJva2F5IjsKPiAr CXVhcnQtaGFzLXJ0c2N0czsKPiArfTsKPiArCj4gKyZ1YXJ0MyB7Cj4gKwlzdGF0dXMgPSAib2th eSI7Cj4gK307Cj4gKwo+ICsmdWFydDQgewo+ICsJc3RhdHVzID0gIm9rYXkiOwo+ICt9Owo+ICsK PiArJnVhcnQ1IHsKPiArCXN0YXR1cyA9ICJva2F5IjsKPiArfTsKPiArCj4gKyZlY3NwaTIgewo+ ICsJc3RhdHVzID0gIm9rYXkiOwo+ICt9Owo+IGRpZmYgLS1naXQgYS9hcmNoL2FybS9ib290L2R0 cy9pbXg2ZGwtZW1jb24uZHRzaSBiL2FyY2gvYXJtL2Jvb3QvZHRzL2lteDZkbC1lbWNvbi5kdHNp Cj4gbmV3IGZpbGUgbW9kZSAxMDA2NDQKPiBpbmRleCAwMDAwMDAwMDAwMDAuLjFlZDYyOWM5NzQ3 ZQo+IC0tLSAvZGV2L251bGwKPiArKysgYi9hcmNoL2FybS9ib290L2R0cy9pbXg2ZGwtZW1jb24u ZHRzaQo+IEBAIC0wLDAgKzEsMjcgQEAKPiArLy8gU1BEWC1MaWNlbnNlLUlkZW50aWZpZXI6IChH UEwtMi4wIG9yIE1JVCkKPiArLyogQ29weXJpZ2h0IChDKSAyMDE4IGVtdHJpb24gR21iSAo+ICsg KiBBdXRob3I6IEphbiBUdWVyayAgPGphbi50dWVya0BlbXRyaW9uLmNvbT4KPiArICovCj4gKwo+ ICsvIHsKPiArCW1vZGVsID0gImVtdHJpb24gU29NIGVtQ09OLU1YNiBTb2xvL0R1YWxMaXRlIjsK PiArCWNvbXBhdGlibGUgPSAiZW10cmlvbixlbWNvbi1teDYiLCAiZnNsLGlteDZkbCI7Cj4gK307 Cj4gKwo+ICsmaW9tdXhjIHsKPiArCXBpbmN0cmxfY3BpMjogY3NpMWdycCB7Cj4gKwkJZnNsLHBp bnMgPSA8Cj4gKwkJCU1YNlFETF9QQURfRUlNX0QxN19fSVBVMV9DU0kxX1BJWENMSwkweDBiMGIx Cj4gKwkJCU1YNlFETF9QQURfRUlNX0VCM19fSVBVMV9DU0kxX0hTWU5DCQkweDFiMGIxCj4gKwkJ CU1YNlFETF9QQURfRUlNX0QyOV9fSVBVMV9DU0kxX1ZTWU5DCQkweDFiMGIxCj4gKwkJCU1YNlFE TF9QQURfRUlNX0ExN19fSVBVMV9DU0kxX0RBVEExMgkweDFiMGIxCj4gKwkJCU1YNlFETF9QQURf RUlNX0QyN19fSVBVMV9DU0kxX0RBVEExMwkweDFiMGIxCj4gKwkJCU1YNlFETF9QQURfRUlNX0Qy Nl9fSVBVMV9DU0kxX0RBVEExNAkweDFiMGIxCj4gKwkJCU1YNlFETF9QQURfRUlNX0QyMF9fSVBV MV9DU0kxX0RBVEExNQkweDFiMGIxCj4gKwkJCU1YNlFETF9QQURfRUlNX0QxOV9fSVBVMV9DU0kx X0RBVEExNgkweDFiMGIxCj4gKwkJCU1YNlFETF9QQURfRUlNX0QxOF9fSVBVMV9DU0kxX0RBVEEx NwkweDFiMGIxCj4gKwkJCU1YNlFETF9QQURfRUlNX0QxNl9fSVBVMV9DU0kxX0RBVEExOAkweDFi MGIxCj4gKwkJCU1YNlFETF9QQURfRUlNX0VCMl9fSVBVMV9DU0kxX0RBVEExOQkweDFiMGIxCj4g KwkJPjsKPiArCX07Cj4gK307Cj4gZGlmZiAtLWdpdCBhL2FyY2gvYXJtL2Jvb3QvZHRzL2lteDZx LWVtY29uLWF2YXJpLmR0cyBiL2FyY2gvYXJtL2Jvb3QvZHRzL2lteDZxLWVtY29uLWF2YXJpLmR0 cwo+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0Cj4gaW5kZXggMDAwMDAwMDAwMDAwLi4wYzg1YjVlZTAx MWMKPiAtLS0gL2Rldi9udWxsCj4gKysrIGIvYXJjaC9hcm0vYm9vdC9kdHMvaW14NnEtZW1jb24t YXZhcmkuZHRzCgpUaGVyZSBhcmUgc28gbWFueSB0aGluZ3MgZHVwbGljYXRlZCBiZXR3ZWVuIGlt eDZkbC1lbWNvbi1hdmFyaS5kdHMgYW5kCmlteDZxLWVtY29uLWF2YXJpLmR0cy4gIENhbiB5b3Ug ZG8gc29tZXRoaW5nIHRvIGF2b2lkIHRoYXQ/Cgo+IEBAIC0wLDAgKzEsMjI0IEBACj4gKy8vIFNQ RFgtTGljZW5zZS1JZGVudGlmaWVyOiAoR1BMLTIuMCBvciBNSVQpCj4gKy8qIENvcHlyaWdodCAo QykgMjAxOCBlbXRyaW9uIEdtYkgKPiArICogQXV0aG9yOiBKYW4gVHVlcmsgIDxqYW4udHVlcmtA ZW10cmlvbi5jb20+Cj4gKyAqLwo+ICsKPiArL2R0cy12MS87Cj4gKyNpbmNsdWRlICJpbXg2cS5k dHNpIgo+ICsjaW5jbHVkZSAiaW14NnFkbC1lbWNvbi5kdHNpIgo+ICsjaW5jbHVkZSAiaW14NnEt ZW1jb24uZHRzaSIgLypJbmNsdWRlIGNhbWVyYTIgcGlubXV4Ki8KPiArCj4gKy8gewo+ICsJbW9k ZWwgPSAiZW10cmlvbiBTb00gZW1DT04tTVg2IER1YWwvUXVhZCBvbiBBdmFyaSI7Cj4gKwljb21w YXRpYmxlID0gImVtdHJpb24sZW1jb24tbXg2LWF2YXJpIiwgImZzbCxpbXg2cSI7Cj4gKwo+ICsJ YWxpYXNlcyB7Cj4gKwkJbW1jMCA9ICZ1c2RoYzM7Cj4gKwkJbW1jMiA9ICZ1c2RoYzE7Cj4gKwkJ bW1jMSA9ICZ1c2RoYzI7Cj4gKwkJbW1jMyA9ICZ1c2RoYzQ7Cj4gKwl9Owo+ICsKPiArCWNob3Nl biB7Cj4gKwkJc3Rkb3V0LXBhdGggPSA8JnVhcnQxPjsKPiArCX07Cj4gKwo+ICsJbWVtb3J5IHsK PiArCQlyZWcgPSA8MHgxMDAwMDAwMCAweDQwMDAwMDAwPjsKPiArCX07Cj4gKwo+ICsJc3VwcGxp ZXMgewo+ICsJCWNvbXBhdGlibGUgPSAic2ltcGxlLWJ1cyI7Cj4gKwkJI2FkZHJlc3MtY2VsbHMg PSA8MT47Cj4gKwkJI3NpemUtY2VsbHMgPSA8MD47Cj4gKwo+ICsJCXdhbGxwbHVnNXAwOiBzdXBw bHlAMCB7Cj4gKwkJCWNvbXBhdGlibGUgPSAicmVndWxhdG9yLWZpeGVkIjsKPiArCQkJcmVnID0g PDA+Owo+ICsJCQlyZWd1bGF0b3ItbmFtZSA9ICJXQUxMLVBMVUciOwo+ICsJCQlyZWd1bGF0b3It bWluLW1pY3Jvdm9sdCA9IDw1MDAwMDAwPjsKPiArCQkJcmVndWxhdG9yLW1heC1taWNyb3ZvbHQg PSA8NTAwMDAwMD47Cj4gKwkJCXJlZ3VsYXRvci1hbHdheXMtb247Cj4gKwkJCXJlZ3VsYXRvci1i b290LW9uOwo+ICsJCX07Cj4gKwo+ICsJCWJhc2UzcDM6IHN1cHBseUAxIHsKPiArCQkJY29tcGF0 aWJsZSA9ICJyZWd1bGF0b3ItZml4ZWQiOwo+ICsJCQlyZWcgPSA8MT47Cj4gKwkJCXZpbi1zdXBw bHkgPSA8JndhbGxwbHVnNXAwPjsKPiArCQkJcmVndWxhdG9yLW5hbWUgPSAiM1YzLWF2YXJpIjsK PiArCQkJcmVndWxhdG9yLW1pbi1taWNyb3ZvbHQgPSA8MzMwMDAwMD47Cj4gKwkJCXJlZ3VsYXRv ci1tYXgtbWljcm92b2x0ID0gPDMzMDAwMDA+Owo+ICsJCQlyZWd1bGF0b3ItYWx3YXlzLW9uOwo+ ICsJCQlyZWd1bGF0b3ItYm9vdC1vbjsKPiArCQl9Owo+ICsKPiArCQliYXNlMXA1OiBzdXBwbHlA MiB7Cj4gKwkJCWNvbXBhdGlibGUgPSAicmVndWxhdG9yLWZpeGVkIjsKPiArCQkJcmVnID0gPDI+ Owo+ICsJCQl2aW4tc3VwcGx5ID0gPCZiYXNlM3AzPjsKPiArCQkJcmVndWxhdG9yLW5hbWUgPSAi MVY1LWF2YXJpIjsKPiArCQkJcmVndWxhdG9yLW1pbi1taWNyb3ZvbHQgPSA8MTUwMDAwMD47Cj4g KwkJCXJlZ3VsYXRvci1tYXgtbWljcm92b2x0ID0gPDE1MDAwMDA+Owo+ICsJCQlyZWd1bGF0b3It YWx3YXlzLW9uOwo+ICsJCQlyZWd1bGF0b3ItYm9vdC1vbjsKPiArCQl9Owo+ICsKPiArCQlyZWdf dXNiX290Zzogb3RndmJ1c0AzIHsKPiArCQkJY29tcGF0aWJsZSA9ICJyZWd1bGF0b3ItZml4ZWQi Owo+ICsJCQlyZWcgPSA8Mz47Cj4gKwkJCXZpbi1zdXBwbHkgPSA8JndhbGxwbHVnNXAwPjsKPiAr CQkJcmVndWxhdG9yLW5hbWUgPSAiT1RHX1ZCVVMiOwo+ICsJCQlyZWd1bGF0b3ItbWluLW1pY3Jv dm9sdCA9IDw1MDAwMDAwPjsKPiArCQkJcmVndWxhdG9yLW1heC1taWNyb3ZvbHQgPSA8NTAwMDAw MD47Cj4gKwkJCWdwaW8gPSA8JmdwaW8xIDggR1BJT19BQ1RJVkVfTE9XPjsKPiArCQkJcmVndWxh dG9yLWFsd2F5cy1vbjsKPiArCQl9Owo+ICsKPiArCX07Cj4gKwo+ICsKPiArCXNuZG9zYzogMTJN SFpvc2Mgewo+ICsJCWNvbXBhdGlibGUgPSAiZml4ZWQtY2xvY2siOwo+ICsJCSNjbG9jay1jZWxs cyA9IDwwPjsKPiArCQljbG9jay1mcmVxdWVuY3kgID0gPDEyMDAwMDAwPjsKPiArCX07Cj4gKwo+ ICsJc291bmQgewo+ICsJCWNvbXBhdGlibGUgPSAiZnNsLGlteC1hdWRpby1zZ3RsNTAwMCI7Cj4g KwkJbW9kZWwgPSAiZW1DT04tYXZhcmktc2d0bDUwMDAiOwo+ICsJCXNzaS1jb250cm9sbGVyID0g PCZzc2kyPjsKPiArCQlhdWRpby1jb2RlYyA9IDwmc2d0bDUwMDA+Owo+ICsJCWF1ZGlvLXJvdXRp bmcgPQo+ICsJCQkiSGVhZHBob25lIEphY2siLCAiSFBfT1VUIjsKPiArCQltdXgtaW50LXBvcnQg PSA8Mj47Cj4gKwkJbXV4LWV4dC1wb3J0ID0gPDM+Owo+ICsJfTsKPiArCj4gK307Cj4gKwo+ICsK PiArJmlvbXV4YyB7Cj4gKwlwaW5jdHJsLW5hbWVzID0gImRlZmF1bHQiOwo+ICsJLypVbnVzZWQg ZW1DT04tTVg2IHBpbmdyb3VwcyBvbiBBVkFSSSBiYXNlYm9hcmQsIGVuYWJsZSBkZWZhdWx0cyov Cj4gKwlwaW5jdHJsLTAgPSA8Cj4gKwkJCQkgJnBpbmN0cmxfZW1jb25fZ3BpbzEgJnBpbmN0cmxf ZW1jb25fZ3BpbzIKPiArCQkJCSAmcGluY3RybF9lbWNvbl9ncGlvMyAmcGluY3RybF9lbWNvbl9n cGlvNQo+ICsJCQkJICZwaW5jdHJsX2VtY29uX2dwaW82ICZwaW5jdHJsX2VtY29uX2dwaW83Cj4g KwkJCQkgJnBpbmN0cmxfZW1jb25fZ3BpbzggJnBpbmN0cmxfZW1jb25faXJxX2EKPiArCQkJCSAm cGluY3RybF9lbWNvbl9pcnFfYiAmcGluY3RybF9lbWNvbl9pcnFfYwo+ICsJCQkJICZwaW5jdHJs X2VtY29uX2lycV9wd3IgJnBpbmN0cmxfbm9yX2ZsYXNoCj4gKwkJCQkgJnBpbmN0cmxfdXNkaGMy Cj4gKwkJCQkgJnBpbmN0cmxfc3BkaWZfb3V0ICAgICAmcGluY3RybF9zcGRpZl9pbgo+ICsJCQkJ ICZwaW5jdHJsX2NwaTEgICAgICAgICAgJnBpbmN0cmxfY3BpMgo+ICsJCQkJPjsKPiArfTsKPiAr Cj4gKyZhdWRtdXggewo+ICsJcGluY3RybC1uYW1lcyA9ICJkZWZhdWx0IjsKPiArCXBpbmN0cmwt MCA9IDwmcGluY3RybF9hdWRtdXg+Owo+ICsJc3RhdHVzID0gIm9rYXkiOwo+ICt9Owo+ICsKPiAr Cj4gKwo+ICsmaTJjMyB7Cj4gKwljbG9jay1mcmVxdWVuY3kgPSA8MTAwMDAwPjsKPiArCXBpbmN0 cmwtbmFtZXMgPSAiZGVmYXVsdCI7Cj4gKwlwaW5jdHJsLTAgPSA8JnBpbmN0cmxfaTJjMz47Cj4g KwlzdGF0dXMgPSAib2theSI7Cj4gKwo+ICsJc2d0bDUwMDA6IGF1ZGlvLWNvZGVjQGEgewo+ICsJ CWNvbXBhdGlibGUgPSAiZnNsLHNndGw1MDAwIjsKPiArCQlyZWcgPSA8MHgwYT47Cj4gKwkJY2xv Y2tzID0gPCZzbmRvc2M+Owo+ICsJCVZEREEtc3VwcGx5ID0gPCZiYXNlM3AzPjsKPiArCQlWRERJ Ty1zdXBwbHkgPSA8JmJhc2UzcDM+Owo+ICsJfTsKPiArCj4gKwlib2FyZElEOiBwY2E4NzU0YUAz YSB7Cj4gKwkJY29tcGF0aWJsZSA9ICJueHAscGNhODU3NCI7Cj4gKwkJcmVnID0gPDB4M2E+Owo+ ICsJCWdwaW8tY29udHJvbGxlcjsKPiArCQkjZ3Bpby1jZWxscyA9IDwxPjsKPiArCX07Cj4gKwo+ ICsJY2FwdG91Y2g6IHRvdWNoc2NyZWVuQDM4IHsKPiArCQljb21wYXRpYmxlID0gImVkdCxlZHQt ZnQ1NDA2IjsKPiArCQlyZWcgPSA8MHgzOD47Cj4gKwkJcGluY3RybC1uYW1lcyA9ICJkZWZhdWx0 IjsKPiArCQlwaW5jdHJsLTAgPSA8JnBpbmN0cmxfaXJxX3RvdWNoMiAmcGluY3RybF9lbWNvbl9n cGlvND47Cj4gKwkJaW50ZXJydXB0LXBhcmVudCA9IDwmZ3BpbzY+Owo+ICsJCWludGVycnVwdHMg PSA8MzEgSVJRX1RZUEVfRURHRV9GQUxMSU5HPjsKPiArCQl3YWtlLWdwaW9zID0gPCZncGlvMiAz IEdQSU9fQUNUSVZFX0hJR0g+Owo+ICsJCXdha2V1cC1zb3VyY2U7Cj4gKwkJc3RhdHVzID0gIm9r YXkiOwo+ICsJfTsKPiArfTsKPiArCj4gKyZzc2kyIHsKPiArCXN0YXR1cyA9ICJva2F5IjsKPiAr fTsKPiArCj4gKyZyZ2JfZW5jb2RlciB7Cj4gKwlzdGF0dXMgPSAib2theSI7Cj4gK307Cj4gKwo+ ICsmcmdiX3BhbmVsIHsKPiArCWNvbXBhdGlibGUgPSAiZWR0LGV0bTA3MDBnMGJkaDYiOwo+ICsJ c3RhdHVzID0gIm9rYXkiOwo+ICt9Owo+ICsKPiArJmkyYzIgewo+ICsJc3RhdHVzID0gIm9rYXki Owo+ICt9Owo+ICsKPiArJmhkbWkgewo+ICsJZGRjLWkyYy1idXMgPSA8JmkyYzI+Owo+ICsJc3Rh dHVzID0gIm9rYXkiOwo+ICt9Owo+ICsKPiArJnVzYmgxIHsKPiArCXN0YXR1cyA9ICJva2F5IjsK PiArfTsKPiArCj4gKyZ1c2JvdGcgewo+ICsJc3RhdHVzID0gIm9rYXkiOwo+ICt9Owo+ICsKPiAr JnBjaWUgewo+ICsJc3RhdHVzID0gIm9rYXkiOwo+ICt9Owo+ICsKPiArJnVzZGhjMSB7Cj4gKwlz dGF0dXMgPSAib2theSI7Cj4gK307Cj4gKwo+ICsmY2FuMSB7Cj4gKwlzdGF0dXMgPSAib2theSI7 Cj4gK307Cj4gKwo+ICsmY2FuMiB7Cj4gKwlzdGF0dXMgPSAib2theSI7Cj4gK307Cj4gKwo+ICsm dWFydDIgewo+ICsJc3RhdHVzID0gIm9rYXkiOwo+ICsJdWFydC1oYXMtcnRzY3RzOwo+ICt9Owo+ ICsKPiArJnVhcnQzIHsKPiArCXN0YXR1cyA9ICJva2F5IjsKPiArfTsKPiArCj4gKyZ1YXJ0NCB7 Cj4gKwlzdGF0dXMgPSAib2theSI7Cj4gK307Cj4gKwo+ICsmdWFydDUgewo+ICsJc3RhdHVzID0g Im9rYXkiOwo+ICt9Owo+ICsKPiArJmVjc3BpMiB7Cj4gKwlzdGF0dXMgPSAib2theSI7Cj4gK307 Cj4gZGlmZiAtLWdpdCBhL2FyY2gvYXJtL2Jvb3QvZHRzL2lteDZxLWVtY29uLmR0c2kgYi9hcmNo L2FybS9ib290L2R0cy9pbXg2cS1lbWNvbi5kdHNpCj4gbmV3IGZpbGUgbW9kZSAxMDA2NDQKPiBp bmRleCAwMDAwMDAwMDAwMDAuLjMzYjNmYmYzZmJhMAo+IC0tLSAvZGV2L251bGwKPiArKysgYi9h cmNoL2FybS9ib290L2R0cy9pbXg2cS1lbWNvbi5kdHNpCj4gQEAgLTAsMCArMSwyNyBAQAo+ICsv LyBTUERYLUxpY2Vuc2UtSWRlbnRpZmllcjogKEdQTC0yLjAgb3IgTUlUKQo+ICsvKiBDb3B5cmln aHQgKEMpIDIwMTggZW10cmlvbiBHbWJICj4gKyAqIEF1dGhvcjogSmFuIFR1ZXJrICA8amFuLnR1 ZXJrQGVtdHJpb24uY29tPgo+ICsgKi8KPiArCj4gKy8gewo+ICsJbW9kZWwgPSAiZW10cmlvbiBT b00gZW1DT04tTVg2IER1YWwvUXVhZCI7Cj4gKwljb21wYXRpYmxlID0gImVtdHJpb24sZW1jb24t bXg2IiwgImZzbCxpbXg2cSI7Cj4gK307Cj4gKwo+ICsmaW9tdXhjIHsKPiArCXBpbmN0cmxfY3Bp MjogY3NpMWdycCB7Cj4gKwkJZnNsLHBpbnMgPSA8Cj4gKwkJCU1YNlFETF9QQURfRUlNX0QxN19f SVBVMl9DU0kxX1BJWENMSwkweDBiMGIxCj4gKwkJCU1YNlFETF9QQURfRUlNX0VCM19fSVBVMl9D U0kxX0hTWU5DCQkweDFiMGIxCj4gKwkJCU1YNlFETF9QQURfRUlNX0QyOV9fSVBVMl9DU0kxX1ZT WU5DCQkweDFiMGIxCj4gKwkJCU1YNlFETF9QQURfRUlNX0ExN19fSVBVMl9DU0kxX0RBVEExMgkw eDFiMGIxCj4gKwkJCU1YNlFETF9QQURfRUlNX0QyN19fSVBVMl9DU0kxX0RBVEExMwkweDFiMGIx Cj4gKwkJCU1YNlFETF9QQURfRUlNX0QyNl9fSVBVMl9DU0kxX0RBVEExNAkweDFiMGIxCj4gKwkJ CU1YNlFETF9QQURfRUlNX0QyMF9fSVBVMl9DU0kxX0RBVEExNQkweDFiMGIxCj4gKwkJCU1YNlFE TF9QQURfRUlNX0QxOV9fSVBVMl9DU0kxX0RBVEExNgkweDFiMGIxCj4gKwkJCU1YNlFETF9QQURf RUlNX0QxOF9fSVBVMl9DU0kxX0RBVEExNwkweDFiMGIxCj4gKwkJCU1YNlFETF9QQURfRUlNX0Qx Nl9fSVBVMl9DU0kxX0RBVEExOAkweDFiMGIxCj4gKwkJCU1YNlFETF9QQURfRUlNX0VCMl9fSVBV Ml9DU0kxX0RBVEExOQkweDFiMGIxCj4gKwkJPjsKPiArCX07Cj4gK307Cj4gZGlmZiAtLWdpdCBh L2FyY2gvYXJtL2Jvb3QvZHRzL2lteDZxZGwtZW1jb24uZHRzaSBiL2FyY2gvYXJtL2Jvb3QvZHRz L2lteDZxZGwtZW1jb24uZHRzaQo+IG5ldyBmaWxlIG1vZGUgMTAwNjQ0Cj4gaW5kZXggMDAwMDAw MDAwMDAwLi41ZjkyOTZkY2UxMzAKPiAtLS0gL2Rldi9udWxsCj4gKysrIGIvYXJjaC9hcm0vYm9v dC9kdHMvaW14NnFkbC1lbWNvbi5kdHNpCj4gQEAgLTAsMCArMSw4MzggQEAKPiArLy8gU1BEWC1M aWNlbnNlLUlkZW50aWZpZXI6IChHUEwtMi4wIG9yIE1JVCkKPiArLyogQ29weXJpZ2h0IChDKSAy MDE4IGVtdHJpb24gR21iSAo+ICsgKiBBdXRob3I6IEphbiBUdWVyayAgPGphbi50dWVya0BlbXRy aW9uLmNvbT4KPiArICovCj4gKwo+ICsjaW5jbHVkZSA8ZHQtYmluZGluZ3MvZ3Bpby9ncGlvLmg+ Cj4gKyNpbmNsdWRlIDxkdC1iaW5kaW5ncy9wd20vcHdtLmg+Cj4gKyNpbmNsdWRlIDxkdC1iaW5k aW5ncy9pbnB1dC9pbnB1dC5oPgo+ICsKPiArLyB7Cj4gKwo+ICsJbW9kZWwgPSAiZW10cmlvbiBT b00gZW1DT04tTVg2IjsKPiArCWNvbXBhdGlibGUgPSAiZW10cmlvbixlbWNvbi1teDYiLCAiZnNs LGlteDZxIiwgImZzbCxpbXg2ZGwiOwo+ICsKPiArCWFsaWFzZXMgewo+ICsJCW1tYzAgPSAmdXNk aGMzOwo+ICsJCW1tYzIgPSAmdXNkaGMxOwo+ICsJCW1tYzEgPSAmdXNkaGMyOwo+ICsJfTsKPiAr Cj4gKwlyZWd1bGF0b3JzIHsKPiArCQljb21wYXRpYmxlID0gInNpbXBsZS1idXMiOwo+ICsJCSNh ZGRyZXNzLWNlbGxzID0gPDE+Owo+ICsJCSNzaXplLWNlbGxzID0gPDA+Owo+ICsKPiArCQlyZWdf cGFyYWxsZWxfZGlzcDogcmVndWxhdG9yQDAgewo+ICsJCQljb21wYXRpYmxlID0gInJlZ3VsYXRv ci1maXhlZCI7Cj4gKwkJCXJlZyA9IDwwPjsKPiArCQkJcGluY3RybC1uYW1lcyA9ICJkZWZhdWx0 IjsKPiArCQkJcGluY3RybC0wID0gPCZwaW5jdHJsX3JnYl9ibF9lbj47Cj4gKwkJCXJlZ3VsYXRv ci1uYW1lID0gIkxDRC1TdXBwbHkiOwo+ICsJCQlyZWd1bGF0b3ItbWluLW1pY3Jvdm9sdCA9IDw1 MDAwMDAwPjsKPiArCQkJcmVndWxhdG9yLW1heC1taWNyb3ZvbHQgPSA8NTAwMDAwMD47Cj4gKwkJ CWdwaW8gPSA8JmdwaW83IDkgR1BJT19BQ1RJVkVfSElHSD47Cj4gKwkJCWVuYWJsZS1hY3RpdmUt aGlnaDsKPiArCQl9Owo+ICsKPiArCQlyZWdfbHZkc19kaXNwOiByZWd1bGF0b3JAMSB7Cj4gKwkJ CWNvbXBhdGlibGUgPSAicmVndWxhdG9yLWZpeGVkIjsKPiArCQkJcmVnID0gPDE+Owo+ICsJCQly ZWd1bGF0b3ItbmFtZSA9ICJMVkRTLVN1cHBseSI7Cj4gKwkJCXJlZ3VsYXRvci1taW4tbWljcm92 b2x0ID0gPDUwMDAwMDA+Owo+ICsJCQlyZWd1bGF0b3ItbWF4LW1pY3Jvdm9sdCA9IDw1MDAwMDAw PjsKPiArCQkJZ3BpbyA9IDwmZ3BpbzcgMTAgR1BJT19BQ1RJVkVfSElHSD47Cj4gKwkJCWVuYWJs ZS1hY3RpdmUtaGlnaDsKPiArCQl9Owo+ICsJfTsKPiArCj4gKwlzb21fbGVkczogbGVkcyB7Cj4g KwkJY29tcGF0aWJsZSA9ICJncGlvLWxlZHMiOwo+ICsJCXBpbmN0cmwtbmFtZXMgPSAiZGVmYXVs dCI7Cj4gKwkJcGluY3RybC0wID0gPCZwaW5jdHJsX3NvbV9sZWRzPjsKPiArCj4gKwkJZ3JlZW4g ewo+ICsJCQlsYWJlbCA9ICJzb206Z3JlZW4iOwo+ICsJCQlncGlvcyA9IDwmZ3BpbzMgMCBHUElP X0FDVElWRV9ISUdIPjsKPiArCQkJbGludXgsZGVmYXVsdC10cmlnZ2VyID0gImhlYXJ0YmVhdCI7 Cj4gKwkJCWRlZmF1bHQtc3RhdGUgPSAib24iOwo+ICsJCX07Cj4gKwo+ICsJCXJlZCB7Cj4gKwkJ CWxhYmVsID0gInNvbTpyZWQiOwo+ICsJCQlncGlvcyA9IDwmZ3BpbzMgMSBHUElPX0FDVElWRV9M T1c+Owo+ICsJCQlkZWZhdWx0LXN0YXRlID0gImtlZXAiOwo+ICsJCX07Cj4gKwo+ICsJfTsKPiAr Cj4gKwlncGlvLWtleXMgewo+ICsJCWNvbXBhdGlibGUgPSAiZ3Bpby1rZXlzIjsKPiArCQlwaW5j dHJsLW5hbWVzID0gImRlZmF1bHQiOwo+ICsJCXBpbmN0cmwtMCA9IDwmcGluY3RybF9lbWNvbl93 YWtlPjsKPiArCj4gKwkJd2FrZSB7Cj4gKwkJCWxhYmVsID0gIldha2UiOwo+ICsJCQlsaW51eCxj b2RlID0gPEtFWV9XQUtFVVA+Owo+ICsJCQlncGlvcyA9IDwmZ3BpbzMgMiBHUElPX0FDVElWRV9M T1c+Owo+ICsJCQl3YWtldXAtc291cmNlOwo+ICsJCX07Cj4gKwl9Owo+ICsKPiArCXB3bV9mYW46 IHB3bS1mYW4gewo+ICsJCWNvbXBhdGlibGUgPSAicHdtLWZhbiI7Cj4gKwkJY29vbGluZy1taW4t c3RhdGUgPSA8MD47Cj4gKwkJY29vbGluZy1tYXgtc3RhdGUgPSA8ND47Cj4gKwkJI2Nvb2xpbmct Y2VsbHMgPSA8Mj47Cj4gKwkJcHdtcyA9IDwmcHdtNCAwIDUwMDAwPjsKPiArCQljb29saW5nLWxl dmVscyA9IDwwIDY0IDEyNyAxOTEgMjU1PjsKPiArCQlzdGF0dXMgPSAiZGlzYWJsZWQiOwo+ICsJ fTsKPiArCj4gKwlyZ2JfZW5jb2RlcjogZGlzcDAgewoKcy9kaXNwMC9kaXNwbGF5Cgo+ICsJCWNv bXBhdGlibGUgPSAiZnNsLGlteC1wYXJhbGxlbC1kaXNwbGF5IjsKPiArCQkjYWRkcmVzcy1jZWxs cyA9IDwxPjsKPiArCQkjc2l6ZS1jZWxscyA9IDwwPjsKPiArCQlwaW5jdHJsLW5hbWVzID0gImRl ZmF1bHQiOwo+ICsJCXBpbmN0cmwtMCA9IDwmcGluY3RybF9yZ2IyNF9kaXNwbGF5PjsKPiArCQlz dGF0dXMgPSAiZGlzYWJsZWQiOwo+ICsKPiArCQlwb3J0QDAgewo+ICsJCQlyZWcgPSA8MD47CgpI YXZlIGEgbmV3bGluZSBiZXR3ZWVuIHByb3BlcnR5IGxpc3QgYW5kIGNoaWxkIG5vZGUuCgo+ICsJ CQlyZ2JfZW5jb2Rlcl9pbjogZW5kcG9pbnQgewo+ICsJCQkJcmVtb3RlLWVuZHBvaW50ID0gPCZp cHUxX2RpMF9kaXNwMD47Cj4gKwkJCX07Cj4gKwkJfTsKPiArCj4gKwkJcG9ydEAxIHsKPiArCQkJ cmVnID0gPDE+Owo+ICsJCQlyZ2JfZW5jb2Rlcl9vdXQ6IGVuZHBvaW50IHsKPiArCQkJCXJlbW90 ZS1lbmRwb2ludCA9IDwmcmdiX3BhbmVsX2luPjsKPiArCQkJfTsKPiArCQl9Owo+ICsJfTsKPiAr Cj4gKwlyZ2JfcGFuZWw6IHBhbmVsIHsKPiArCQliYWNrbGlnaHQgPSA8JnJnYl9iYWNrbGlnaHQ+ Owo+ICsJCXBvd2VyLXN1cHBseSA9IDwmcmVnX3BhcmFsbGVsX2Rpc3A+Owo+ICsJCXBvcnQgewo+ ICsJCQlyZ2JfcGFuZWxfaW46IGVuZHBvaW50IHsKPiArCQkJCXJlbW90ZS1lbmRwb2ludCA9IDwm cmdiX2VuY29kZXJfb3V0PjsKPiArCQkJfTsKPiArCQl9Owo+ICsJfTsKPiArCj4gKwlyZ2JfYmFj a2xpZ2h0OiByZ2ItYmFja2xpZ2h0IHsKPiArCQljb21wYXRpYmxlID0gInB3bS1iYWNrbGlnaHQi Owo+ICsJCXBpbmN0cmwtbmFtZXMgPSAiZGVmYXVsdCI7Cj4gKwkJcGluY3RybC0wID0gPCZwaW5j dHJsX3JnYl9ibD47Cj4gKwkJZW5hYmxlLWdwaW9zID0gPCZncGlvNiA4IEdQSU9fQUNUSVZFX0hJ R0g+Owo+ICsJCXB3bXMgPSA8JnB3bTMgMCA1MDAwMDAwPjsKPiArCQlicmlnaHRuZXNzLWxldmVs cyA9IDwyNTAgMTc2IDE2MCAxNDQgMTI4IDExMgo+ICsJCQkJCQkJOTYgODAgNjQgNDggMzIgMTYg OCAxCj4gKwkJCQkJCQk+OwoKQnJva2VuIGluZGVudC4KCj4gKwkJZGVmYXVsdC1icmlnaHRuZXNz LWxldmVsID0gPDEzPjsKPiArCQlzdGF0dXMgPSAib2theSI7Cj4gKwl9Owo+ICsKPiArCWx2ZHNf YmFja2xpZ2h0OiBsdmRzLWJhY2tsaWdodCB7Cj4gKwkJY29tcGF0aWJsZSA9ICJwd20tYmFja2xp Z2h0IjsKPiArCQlwaW5jdHJsLW5hbWVzID0gImRlZmF1bHQiOwo+ICsJCXBpbmN0cmwtMCA9IDwm cGluY3RybF9sdmRzX2JsPjsKPiArCQllbmFibGUtZ3Bpb3MgPSA8JmdwaW82IDkgR1BJT19BQ1RJ VkVfSElHSD47Cj4gKwkJcHdtcyA9IDwmcHdtMSAwIDUwMDAwPjsKPiArCQlicmlnaHRuZXNzLWxl dmVscyA9IDwwIDQgOCAxNiAzMiA2NCA4MCA5NiAxMTIKPiArCQkJCQkJCTEyOCAxNDQgMTYwIDE3 NiAyNTAKPiArCQkJCQkJCT47Cj4gKwkJZGVmYXVsdC1icmlnaHRuZXNzLWxldmVsID0gPDEzPjsK PiArCQlzdGF0dXMgPSAib2theSI7Cj4gKwl9Owo+ICt9Owo+ICsKPiArCj4gKyZpb211eGMgewo+ ICsKPiArCXBpbmN0cmxfc2VjdXJlOiBzZWN1cmVncnAgewoKVW51c2VkPwoKPiArCQlmc2wscGlu cyA9IDwKPiArCQkJTVg2UURMX1BBRF9HUElPXzE4X19HUElPN19JTzEzCQkJMHgxYjBiMQo+ICsJ CT47Cj4gKwl9Owo+ICsKPiArCXBpbmN0cmxfdWFydDE6IHVhcnQxZ3JwIHsKPiArCQlmc2wscGlu cyA9IDwKPiArCQkJTVg2UURMX1BBRF9DU0kwX0RBVDEwX19VQVJUMV9UWF9EQVRBCTB4MWIwYjEK PiArCQkJTVg2UURMX1BBRF9DU0kwX0RBVDExX19VQVJUMV9SWF9EQVRBCTB4MWIwYjEKPiArCQk+ Owo+ICsJfTsKPiArCj4gKwlwaW5jdHJsX3VhcnQyOiB1YXJ0MmdycCB7Cj4gKwkJZnNsLHBpbnMg PSA8Cj4gKwkJCU1YNlFETF9QQURfU0Q0X0RBVDVfX1VBUlQyX1JUU19CCQkweDFiMGIxCj4gKwkJ CU1YNlFETF9QQURfU0Q0X0RBVDZfX1VBUlQyX0NUU19CCQkweDFiMGIxCj4gKwkJCU1YNlFETF9Q QURfU0Q0X0RBVDdfX1VBUlQyX1RYX0RBVEEJCTB4MWIwYjEKPiArCQkJTVg2UURMX1BBRF9TRDRf REFUNF9fVUFSVDJfUlhfREFUQQkJMHgxYjBiMQo+ICsJCT47Cj4gKwl9Owo+ICsKPiArCXBpbmN0 cmxfdWFydDM6IHVhcnQzZ3JwIHsKPiArCQlmc2wscGlucyA9IDwKPiArCQkJTVg2UURMX1BBRF9F SU1fRDI0X19VQVJUM19UWF9EQVRBCQkweDFiMGIxCj4gKwkJCU1YNlFETF9QQURfRUlNX0QyNV9f VUFSVDNfUlhfREFUQQkJMHgxYjBiMQo+ICsJCT47Cj4gKwl9Owo+ICsKPiArCXBpbmN0cmxfdWFy dDQ6IHVhcnQ0Z3JwIHsKPiArCQlmc2wscGlucyA9IDwKPiArCQkJTVg2UURMX1BBRF9LRVlfQ09M MF9fVUFSVDRfVFhfREFUQQkJMHgxYjBiMQo+ICsJCQlNWDZRRExfUEFEX0tFWV9ST1cwX19VQVJU NF9SWF9EQVRBCQkweDFiMGIxCj4gKwkJPjsKPiArCX07Cj4gKwo+ICsJcGluY3RybF91YXJ0NTog dWFydDVncnAgewo+ICsJCWZzbCxwaW5zID0gPAo+ICsJCQlNWDZRRExfUEFEX0tFWV9DT0wxX19V QVJUNV9UWF9EQVRBCQkweDFiMGIxCj4gKwkJCU1YNlFETF9QQURfS0VZX1JPVzFfX1VBUlQ1X1JY X0RBVEEJCTB4MWIwYjEKPiArCQk+Owo+ICsJfTsKPiArCj4gKwlwaW5jdHJsX2VtY29uX2dwaW8x OiBlbWNvbmdwaW8xIHsKPiArCQlmc2wscGlucyA9IDwKPiArCQkJTVg2UURMX1BBRF9OQU5ERl9E MF9fR1BJTzJfSU8wMAkJCTB4MGIwYjEKPiArCQk+Owo+ICsJfTsKClRyeSB0byBrZWVwIHRoZXNl IHBpbmN0cmwgZW50cmllcyBhbHBoYWJldGljYWxseSBzb3J0ZWQuCgo+ICsKPiArCXBpbmN0cmxf ZW1jb25fZ3BpbzI6IGVtY29uZ3BpbzIgewo+ICsJCWZzbCxwaW5zID0gPAo+ICsJCQlNWDZRRExf UEFEX05BTkRGX0QxX19HUElPMl9JTzAxCQkJMHgwYjBiMQo+ICsJCT47Cj4gKwl9Owo+ICsKPiAr CXBpbmN0cmxfZW1jb25fZ3BpbzM6IGVtY29uZ3BpbzMgewo+ICsJCWZzbCxwaW5zID0gPAo+ICsJ CQlNWDZRRExfUEFEX05BTkRGX0QyX19HUElPMl9JTzAyCQkJMHgwYjBiMQo+ICsJCT47Cj4gKwl9 Owo+ICsKPiArCXBpbmN0cmxfZW1jb25fZ3BpbzQ6IGVtY29uZ3BpbzQgewo+ICsJCWZzbCxwaW5z ID0gPAo+ICsJCQlNWDZRRExfUEFEX05BTkRGX0QzX19HUElPMl9JTzAzCQkJMHgwYjBiMQo+ICsJ CT47Cj4gKwl9Owo+ICsKPiArCXBpbmN0cmxfZW1jb25fZ3BpbzU6IGVtY29uZ3BpbzUgewo+ICsJ CWZzbCxwaW5zID0gPAo+ICsJCQlNWDZRRExfUEFEX05BTkRGX0Q0X19HUElPMl9JTzA0CQkJMHgw YjBiMQo+ICsJCT47Cj4gKwl9Owo+ICsKPiArCXBpbmN0cmxfZW1jb25fZ3BpbzY6IGVtY29uZ3Bp bzYgewo+ICsJCWZzbCxwaW5zID0gPAo+ICsJCQlNWDZRRExfUEFEX05BTkRGX0Q1X19HUElPMl9J TzA1CQkJMHgwYjBiMQo+ICsJCT47Cj4gKwl9Owo+ICsKPiArCXBpbmN0cmxfZW1jb25fZ3Bpbzc6 IGVtY29uZ3Bpbzcgewo+ICsJCWZzbCxwaW5zID0gPAo+ICsJCQlNWDZRRExfUEFEX05BTkRGX0Q2 X19HUElPMl9JTzA2CQkJMHgwYjBiMQo+ICsJCT47Cj4gKwl9Owo+ICsKPiArCXBpbmN0cmxfZW1j b25fZ3Bpbzg6IGVtY29uZ3Bpbzggewo+ICsJCWZzbCxwaW5zID0gPAo+ICsJCQlNWDZRRExfUEFE X05BTkRGX0Q3X19HUElPMl9JTzA3CQkJMHgwYjBiMQo+ICsJCT47Cj4gKwl9Owo+ICsKPiArCXBp bmN0cmxfZW1jb25faXJxX2E6IGVtY29uaXJxYSB7Cj4gKwkJZnNsLHBpbnMgPSA8Cj4gKwkJCU1Y NlFETF9QQURfTkFOREZfQ0xFX19HUElPNl9JTzA3CQkweDBiMGIxCj4gKwkJPjsKPiArCX07Cj4g Kwo+ICsJcGluY3RybF9lbWNvbl9pcnFfYjogZW1jb25pcnFiIHsKPiArCQlmc2wscGlucyA9IDwK PiArCQkJTVg2UURMX1BBRF9OQU5ERl9DUzJfX0dQSU82X0lPMTUJCTB4MGIwYjEKPiArCQk+Owo+ ICsJfTsKPiArCj4gKwlwaW5jdHJsX2VtY29uX2lycV9jOiBlbWNvbmlycWMgewo+ICsJCWZzbCxw aW5zID0gPAo+ICsJCQlNWDZRRExfUEFEX05BTkRGX0NTM19fR1BJTzZfSU8xNgkJMHgwYjBiMQo+ ICsJCT47Cj4gKwl9Owo+ICsKPiArCXBpbmN0cmxfZW1jb25fd2FrZTogZW1jb253YWtlIHsKPiAr CQlmc2wscGlucyA9IDwKPiArCQkJTVg2UURMX1BBRF9FSU1fREEyX19HUElPM19JTzAyCQkJMHgx YjBiMQo+ICsJCT47Cj4gKwl9Owo+ICsKPiArCXBpbmN0cmxfZW1jb25faXJxX3B3cjogZW1jb25p cnFwd3Igewo+ICsJCWZzbCxwaW5zID0gPAo+ICsJCQlNWDZRRExfUEFEX0VJTV9EMjNfX0dQSU8z X0lPMjMJCQkweDBiMGIxCj4gKwkJPjsKPiArCX07Cj4gKwo+ICsJcGluY3RybF9zb21fbGVkczog c29tbGVkZ3JwIHsKPiArCQlmc2wscGlucyA9IDwKPiArCQkJTVg2UURMX1BBRF9FSU1fREEwX19H UElPM19JTzAwCQkJMHgwYjBiMQo+ICsJCQlNWDZRRExfUEFEX0VJTV9EQTFfX0dQSU8zX0lPMDEJ CQkweDBiMGIxCj4gKwkJPjsKPiArCX07Cj4gKwo+ICsJcGluY3RybF9ub3JfZmxhc2g6IG5vcmZs YXNoZ3JwIHsKPiArCQlmc2wscGlucyA9IDwKPiArCQkJTVg2UURMX1BBRF9OQU5ERl9DUzBfX0dQ SU82X0lPMTEJCTB4MWIwYjEKPiArCQkJTVg2UURMX1BBRF9FSU1fRDIxX19FQ1NQSTRfU0NMSwkJ CTB4MTAwYjEKPiArCQkJTVg2UURMX1BBRF9FSU1fRDI4X19FQ1NQSTRfTU9TSQkJCTB4MTAwYjEK PiArCQkJTVg2UURMX1BBRF9FSU1fRDIyX19FQ1NQSTRfTUlTTwkJCTB4MTAwYjEKPiArCQkJTVg2 UURMX1BBRF9FSU1fQTI1X19HUElPNV9JTzAyCQkJMHgxMDBiMQo+ICsJCT47Cj4gKwl9Owo+ICsK PiArCXBpbmN0cmxfZWNzcGkyOiBlY3NwaTJncnAgewo+ICsJCWZzbCxwaW5zID0gPAo+ICsJCQlN WDZRRExfUEFEX0VJTV9DUzBfX0VDU1BJMl9TQ0xLCQkJMHgxMDBiMQo+ICsJCQlNWDZRRExfUEFE X0VJTV9DUzFfX0VDU1BJMl9NT1NJCQkJMHgxMDBiMQo+ICsJCQlNWDZRRExfUEFEX0VJTV9PRV9f RUNTUEkyX01JU08JCQkweDEwMGIxCj4gKwkJCU1YNlFETF9QQURfRUlNX0xCQV9fR1BJTzJfSU8y NwkJCTB4MTAwYjEKPiArCQkJTVg2UURMX1BBRF9FSU1fUldfX0dQSU8yX0lPMjYJCQkweDEwMGIx Cj4gKwkJPjsKPiArCX07Cj4gKwo+ICsJcGluY3RybF9wd21fZmFuOiBwd21mYW4gewo+ICsJCWZz bCxwaW5zID0gPAo+ICsJCQlNWDZRRExfUEFEX1NENF9EQVQyX19QV000X09VVAkJCTB4MGIwYjEK PiArCQk+Owo+ICsJfTsKPiArCj4gKwlwaW5jdHJsX2NhbjE6IGNhbjFncnAgewo+ICsJCWZzbCxw aW5zID0gPAo+ICsJCQlNWDZRRExfUEFEX0tFWV9DT0wyX19GTEVYQ0FOMV9UWAkJMHgxYjBiMQo+ ICsJCQlNWDZRRExfUEFEX0tFWV9ST1cyX19GTEVYQ0FOMV9SWAkJMHgxYjBiMQo+ICsJCT47Cj4g Kwl9Owo+ICsKPiArCXBpbmN0cmxfY2FuMjogY2FuMmdycCB7Cj4gKwkJZnNsLHBpbnMgPSA8Cj4g KwkJCU1YNlFETF9QQURfS0VZX0NPTDRfX0ZMRVhDQU4yX1RYCQkweDFiMGIxCj4gKwkJCU1YNlFE TF9QQURfS0VZX1JPVzRfX0ZMRVhDQU4yX1JYCQkweDFiMGIxCj4gKwkJPjsKPiArCX07Cj4gKwo+ ICsJcGluY3RybF9zcGRpZl9vdXQ6IHNwZGlmb3V0IHsKPiArCQlmc2wscGlucyA9IDwKPiArCQkJ TVg2UURMX1BBRF9HUElPXzE5X19TUERJRl9PVVQJCQkweDEzMDkxCj4gKwkJPjsKPiArCX07Cj4g Kwo+ICsJcGluY3RybF9zcGRpZl9pbjogc3BkaWZpbiB7Cj4gKwkJZnNsLHBpbnMgPSA8Cj4gKwkJ CU1YNlFETF9QQURfR1BJT18xNl9fU1BESUZfSU4JCQkweDFiMGIwCj4gKwkJPjsKPiArCX07Cj4g Kwo+ICsJcGluY3RybF9jcGkxOiBjc2kwZ3JwIHsKPiArCQlmc2wscGlucyA9IDwKPiArCQkJTVg2 UURMX1BBRF9DU0kwX1BJWENMS19fSVBVMV9DU0kwX1BJWENMSyAweGIwYjEKPiArCQkJTVg2UURM X1BBRF9DU0kwX01DTEtfX0lQVTFfQ1NJMF9IU1lOQwkweDFiMGIxCj4gKwkJCU1YNlFETF9QQURf Q1NJMF9WU1lOQ19fSVBVMV9DU0kwX1ZTWU5DCTB4MWIwYjEKPiArCQkJTVg2UURMX1BBRF9DU0kw X0RBVDEyX19JUFUxX0NTSTBfREFUQTEyIDB4MWIwYjEKPiArCQkJTVg2UURMX1BBRF9DU0kwX0RB VDEzX19JUFUxX0NTSTBfREFUQTEzIDB4MWIwYjEKPiArCQkJTVg2UURMX1BBRF9DU0kwX0RBVDE0 X19JUFUxX0NTSTBfREFUQTE0IDB4MWIwYjEKPiArCQkJTVg2UURMX1BBRF9DU0kwX0RBVDE1X19J UFUxX0NTSTBfREFUQTE1IDB4MWIwYjEKPiArCQkJTVg2UURMX1BBRF9DU0kwX0RBVDE2X19JUFUx X0NTSTBfREFUQTE2IDB4MWIwYjEKPiArCQkJTVg2UURMX1BBRF9DU0kwX0RBVDE3X19JUFUxX0NT STBfREFUQTE3IDB4MWIwYjEKPiArCQkJTVg2UURMX1BBRF9DU0kwX0RBVDE4X19JUFUxX0NTSTBf REFUQTE4IDB4MWIwYjEKPiArCQkJTVg2UURMX1BBRF9DU0kwX0RBVDE5X19JUFUxX0NTSTBfREFU QTE5IDB4MWIwYjEKPiArCQk+Owo+ICsJfTsKPiArCj4gKwkvKmNhbWVyYTItcGluY3RybCBpcyBp biBpbXg2cS1lbWNvbi5kdHNpIG9yIGlteDZkbC1lbWNvbi5kdHNpKi8KPiArCj4gKwlwaW5jdHJs X3BjaWVfY3RybDogcGNpZWdycCB7Cj4gKwkJZnNsLHBpbnMgPSA8Cj4gKwkJCU1YNlFETF9QQURf RUlNX0ExNl9fR1BJTzJfSU8yMgkJCTB4MWIwYjEKPiArCQkJTVg2UURMX1BBRF9HUElPXzE3X19H UElPN19JTzEyCQkJMHgxYjBiMQo+ICsJCT47Cj4gKwl9Owo+ICsKPiArCXBpbmN0cmxfYXVkbXV4 OiBhdWRtdXggewo+ICsJCWZzbCxwaW5zID0gPAo+ICsJCQlNWDZRRExfUEFEX0NTSTBfREFUN19f QVVEM19SWEQJCQkweDEzMGIwCj4gKwkJCU1YNlFETF9QQURfQ1NJMF9EQVQ0X19BVUQzX1RYQwkJ CTB4MWIwNjAKPiArCQkJTVg2UURMX1BBRF9DU0kwX0RBVDVfX0FVRDNfVFhECQkJMHgxMzBCMAo+ ICsJCQlNWDZRRExfUEFEX0NTSTBfREFUNl9fQVVEM19UWEZTCQkJMHgxYjA2MAo+ICsJCT47Cj4g Kwl9Owo+ICsKPiArCXBpbmN0cmxfaTJjMTogaTJjMWdycCB7Cj4gKwkJZnNsLHBpbnMgPSA8Cj4g KwkJCU1YNlFETF9QQURfQ1NJMF9EQVQ4X19JMkMxX1NEQQkJMHg0MDAxYjhiMQo+ICsJCQlNWDZR RExfUEFEX0NTSTBfREFUOV9fSTJDMV9TQ0wJCTB4NDAwMWI4YjEKPiArCQk+Owo+ICsJfTsKPiAr Cj4gKwlwaW5jdHJsX2kyYzI6IGkyYzJncnAgewo+ICsJCWZzbCxwaW5zID0gPAo+ICsJCQlNWDZR RExfUEFEX0tFWV9DT0wzX19JMkMyX1NDTAkJMHg0MDAxYjhiMQo+ICsJCQlNWDZRRExfUEFEX0tF WV9ST1czX19JMkMyX1NEQQkJMHg0MDAxYjhiMQo+ICsJCT47Cj4gKwl9Owo+ICsKPiArCXBpbmN0 cmxfaTJjMzogaTJjM2dycCB7Cj4gKwkJZnNsLHBpbnMgPSA8Cj4gKwkJCU1YNlFETF9QQURfR1BJ T18zX19JMkMzX1NDTAkJMHg0MDAwYjA3MAo+ICsJCQlNWDZRRExfUEFEX0dQSU9fNl9fSTJDM19T REEJCTB4NDAwMWI4NzAKPiArCQk+Owo+ICsJfTsKPiArCj4gKwlwaW5jdHJsX3BtaWM6IHBtaWNn cnAgewo+ICsJCWZzbCxwaW5zID0gPAo+ICsJCQlNWDZRRExfUEFEX1NENF9EQVQwX19HUElPMl9J TzA4CQkJMHgwYjBiMQo+ICsJCT47Cj4gKwl9Owo+ICsKPiArCXBpbmN0cmxfdXNiX2hvc3QxOiB1 c2JoZ3JwIHsKPiArCQlmc2wscGlucyA9IDwKPiArCQkJTVg2UURMX1BBRF9FSU1fRDMxX19VU0Jf SDFfUFdSCQkJMHgxQjA1OAo+ICsJCQlNWDZRRExfUEFEX0VJTV9EMzBfX1VTQl9IMV9PQwkJCTB4 MUIwNTgKPiArCQk+Owo+ICsJfTsKPiArCj4gKwlwaW5jdHJsX3VzYl9vdGc6IHVzYm90Z2dycCB7 Cj4gKwkJZnNsLHBpbnMgPSA8Cj4gKwkJCU1YNlFETF9QQURfRU5FVF9SWF9FUl9fVVNCX09UR19J RAkJMHgxNzA1OQo+ICsJCQlNWDZRRExfUEFEX0dQSU9fN19fR1BJTzFfSU8wNwkJCTB4MTcwNTkK PiArCQkJTVg2UURMX1BBRF9HUElPXzhfX0dQSU8xX0lPMDgJCQkweDE3MDU5Cj4gKwkJPjsKPiAr CX07Cj4gKwo+ICsJcGluY3RybF9sdmRzX3JlZzogbHZkc3JlZ2dycCB7Cj4gKwkJZnNsLHBpbnMg PSA8Cj4gKwkJCU1YNlFETF9QQURfU0Q0X0NMS19fR1BJTzdfSU8xMAkJCTB4MGIwYjEKPiArCQk+ Owo+ICsJfTsKPiArCj4gKwlwaW5jdHJsX2x2ZHNfYmw6IGx2ZHNiYWNrbGlnaHRncnAgewo+ICsJ CWZzbCxwaW5zID0gPAo+ICsJCQlNWDZRRExfUEFEX0dQSU9fOV9fUFdNMV9PVVQJCQkweDBiMGIx Cj4gKwkJCU1YNlFETF9QQURfTkFOREZfV1BfQl9fR1BJTzZfSU8wOQkJMHgwYjBiMQo+ICsJCT47 Cj4gKwl9Owo+ICsKPiArCXBpbmN0cmxfaXJxX3RvdWNoMTogaXJxdG91Y2gxIHsKPiArCQlmc2ws cGlucyA9IDwKPiArCQkJTVg2UURMX1BBRF9HUElPXzVfX0dQSU8xX0lPMDUJCQkweDBiMGIxCj4g KwkJPjsKPiArCX07Cj4gKwo+ICsJcGluY3RybF9yZ2JfYmxfZW46IHJnYmVuYWJsZSB7Cj4gKwkJ ZnNsLHBpbnMgPSA8Cj4gKwkJCU1YNlFETF9QQURfU0Q0X0NNRF9fR1BJTzdfSU8wOQkJCTB4MGIw YjEKPiArCQk+Owo+ICsJfTsKPiArCj4gKwlwaW5jdHJsX2lycV90b3VjaDI6IGlycXRvdWNoMiB7 Cj4gKwkJZnNsLHBpbnMgPSA8Cj4gKwkJCU1YNlFETF9QQURfRUlNX0JDTEtfX0dQSU82X0lPMzEJ CQkweDBiMGIxCj4gKwkJPjsKPiArCX07Cj4gKwo+ICsJcGluY3RybF9yZ2JfYmw6IHJnYmJhY2ts aWdodGdycCB7Cj4gKwkJZnNsLHBpbnMgPSA8Cj4gKwkJCU1YNlFETF9QQURfU0Q0X0RBVDFfX1BX TTNfT1VUCQkJMHgwYjBiMQo+ICsJCQlNWDZRRExfUEFEX05BTkRGX0FMRV9fR1BJTzZfSU8wOAkJ MHgwYjBiMQo+ICsJCT47Cj4gKwl9Owo+ICsKPiArCXBpbmN0cmxfcmdiMjRfZGlzcGxheTogcmdi Z3JwIHsKPiArCQlmc2wscGlucyA9IDwKPiArCQkJTVg2UURMX1BBRF9ESTBfRElTUF9DTEtfX0lQ VTFfREkwX0RJU1BfQ0xLIDB4MTAKPiArCQkJTVg2UURMX1BBRF9ESTBfUElOMTVfX0lQVTFfREkw X1BJTjE1ICAgICAgIDB4MTAKPiArCQkJTVg2UURMX1BBRF9ESTBfUElOMl9fSVBVMV9ESTBfUElO MDIgICAgICAgIDB4MTAKPiArCQkJTVg2UURMX1BBRF9ESTBfUElOM19fSVBVMV9ESTBfUElOMDMg ICAgICAgIDB4MTAKPiArCQkJTVg2UURMX1BBRF9ESVNQMF9EQVQwX19JUFUxX0RJU1AwX0RBVEEw MCAgIDB4MTAKPiArCQkJTVg2UURMX1BBRF9ESVNQMF9EQVQxX19JUFUxX0RJU1AwX0RBVEEwMSAg IDB4MTAKPiArCQkJTVg2UURMX1BBRF9ESVNQMF9EQVQyX19JUFUxX0RJU1AwX0RBVEEwMiAgIDB4 MTAKPiArCQkJTVg2UURMX1BBRF9ESVNQMF9EQVQzX19JUFUxX0RJU1AwX0RBVEEwMyAgIDB4MTAK PiArCQkJTVg2UURMX1BBRF9ESVNQMF9EQVQ0X19JUFUxX0RJU1AwX0RBVEEwNCAgIDB4MTAKPiAr CQkJTVg2UURMX1BBRF9ESVNQMF9EQVQ1X19JUFUxX0RJU1AwX0RBVEEwNSAgIDB4MTAKPiArCQkJ TVg2UURMX1BBRF9ESVNQMF9EQVQ2X19JUFUxX0RJU1AwX0RBVEEwNiAgIDB4MTAKPiArCQkJTVg2 UURMX1BBRF9ESVNQMF9EQVQ3X19JUFUxX0RJU1AwX0RBVEEwNyAgIDB4MTAKPiArCQkJTVg2UURM X1BBRF9ESVNQMF9EQVQ4X19JUFUxX0RJU1AwX0RBVEEwOCAgIDB4MTAKPiArCQkJTVg2UURMX1BB RF9ESVNQMF9EQVQ5X19JUFUxX0RJU1AwX0RBVEEwOSAgIDB4MTAKPiArCQkJTVg2UURMX1BBRF9E SVNQMF9EQVQxMF9fSVBVMV9ESVNQMF9EQVRBMTAgIDB4MTAKPiArCQkJTVg2UURMX1BBRF9ESVNQ MF9EQVQxMV9fSVBVMV9ESVNQMF9EQVRBMTEgIDB4MTAKPiArCQkJTVg2UURMX1BBRF9ESVNQMF9E QVQxMl9fSVBVMV9ESVNQMF9EQVRBMTIgIDB4MTAKPiArCQkJTVg2UURMX1BBRF9ESVNQMF9EQVQx M19fSVBVMV9ESVNQMF9EQVRBMTMgIDB4MTAKPiArCQkJTVg2UURMX1BBRF9ESVNQMF9EQVQxNF9f SVBVMV9ESVNQMF9EQVRBMTQgIDB4MTAKPiArCQkJTVg2UURMX1BBRF9ESVNQMF9EQVQxNV9fSVBV MV9ESVNQMF9EQVRBMTUgIDB4MTAKPiArCQkJTVg2UURMX1BBRF9ESVNQMF9EQVQxNl9fSVBVMV9E SVNQMF9EQVRBMTYgIDB4MTAKPiArCQkJTVg2UURMX1BBRF9ESVNQMF9EQVQxN19fSVBVMV9ESVNQ MF9EQVRBMTcgIDB4MTAKPiArCQkJTVg2UURMX1BBRF9ESVNQMF9EQVQxOF9fSVBVMV9ESVNQMF9E QVRBMTggIDB4MTAKPiArCQkJTVg2UURMX1BBRF9ESVNQMF9EQVQxOV9fSVBVMV9ESVNQMF9EQVRB MTkgIDB4MTAKPiArCQkJTVg2UURMX1BBRF9ESVNQMF9EQVQyMF9fSVBVMV9ESVNQMF9EQVRBMjAg IDB4MTAKPiArCQkJTVg2UURMX1BBRF9ESVNQMF9EQVQyMV9fSVBVMV9ESVNQMF9EQVRBMjEgIDB4 MTAKPiArCQkJTVg2UURMX1BBRF9ESVNQMF9EQVQyMl9fSVBVMV9ESVNQMF9EQVRBMjIgIDB4MTAK PiArCQkJTVg2UURMX1BBRF9ESVNQMF9EQVQyM19fSVBVMV9ESVNQMF9EQVRBMjMgIDB4MTAKPiAr CQk+Owo+ICsJfTsKPiArCj4gKwlwaW5jdHJsX2VuZXQ6IGVuZXRncnAgewo+ICsJCWZzbCxwaW5z ID0gPAo+ICsJCQlNWDZRRExfUEFEX0VORVRfTURJT19fRU5FVF9NRElPCQkJMHgxYjAzMAo+ICsJ CQlNWDZRRExfUEFEX0VORVRfTURDX19FTkVUX01EQwkJCTB4MWIwMzAKPiArCQkJTVg2UURMX1BB RF9SR01JSV9UWENfX1JHTUlJX1RYQwkJCTB4MWIwMzAKPiArCQkJTVg2UURMX1BBRF9SR01JSV9U RDBfX1JHTUlJX1REMAkJCTB4MWIwMzAKPiArCQkJTVg2UURMX1BBRF9SR01JSV9URDFfX1JHTUlJ X1REMQkJCTB4MWIwMzAKPiArCQkJTVg2UURMX1BBRF9SR01JSV9URDJfX1JHTUlJX1REMgkJCTB4 MWIwMzAKPiArCQkJTVg2UURMX1BBRF9SR01JSV9URDNfX1JHTUlJX1REMwkJCTB4MWIwMzAKPiAr CQkJTVg2UURMX1BBRF9SR01JSV9UWF9DVExfX1JHTUlJX1RYX0NUTAkweDFiMDMwCj4gKwkJCU1Y NlFETF9QQURfRU5FVF9SRUZfQ0xLX19FTkVUX1RYX0NMSwkweDQwMDFhMGIxCj4gKwkJCU1YNlFE TF9QQURfUkdNSUlfUlhDX19SR01JSV9SWEMJCQkweDFiMDMwCj4gKwkJCU1YNlFETF9QQURfUkdN SUlfUkQwX19SR01JSV9SRDAJCQkweDFiMDMwCj4gKwkJCU1YNlFETF9QQURfUkdNSUlfUkQxX19S R01JSV9SRDEJCQkweDFiMDMwCj4gKwkJCU1YNlFETF9QQURfUkdNSUlfUkQyX19SR01JSV9SRDIJ CQkweDFiMDMwCj4gKwkJCU1YNlFETF9QQURfUkdNSUlfUkQzX19SR01JSV9SRDMJCQkweDFiMDMw Cj4gKwkJCU1YNlFETF9QQURfUkdNSUlfUlhfQ1RMX19SR01JSV9SWF9DVEwJMHgxYjBiMAo+ICsJ CQlNWDZRRExfUEFEX0NTSTBfREFUQV9FTl9fR1BJTzVfSU8yMAkJMHgxYjA1OAo+ICsJCQlNWDZR RExfUEFEX0VORVRfVFhEMF9fR1BJTzFfSU8zMAkJMHgxYjBiMAo+ICsJCSA+Owo+ICsJfTsKPiAr Cj4gKwo+ICsJcGluY3RybF91c2RoYzM6IHVzZGhjM2dycCB7Cj4gKwkJZnNsLHBpbnMgPSA8Cj4g KwkJCU1YNlFETF9QQURfU0QzX0NNRF9fU0QzX0NNRAkJCTB4MTcwNTkKPiArCQkJTVg2UURMX1BB RF9TRDNfQ0xLX19TRDNfQ0xLCQkJMHgxMDA1OQo+ICsJCQlNWDZRRExfUEFEX1NEM19EQVQwX19T RDNfREFUQTAJCQkweDE3MDU5Cj4gKwkJCU1YNlFETF9QQURfU0QzX0RBVDFfX1NEM19EQVRBMQkJ CTB4MTcwNTkKPiArCQkJTVg2UURMX1BBRF9TRDNfREFUMl9fU0QzX0RBVEEyCQkJMHgxNzA1OQo+ ICsJCQlNWDZRRExfUEFEX1NEM19EQVQzX19TRDNfREFUQTMJCQkweDE3MDU5Cj4gKwkJCU1YNlFE TF9QQURfU0QzX0RBVDRfX1NEM19EQVRBNAkJCTB4MTcwNTkKPiArCQkJTVg2UURMX1BBRF9TRDNf REFUNV9fU0QzX0RBVEE1CQkJMHgxNzA1OQo+ICsJCQlNWDZRRExfUEFEX1NEM19EQVQ2X19TRDNf REFUQTYJCQkweDE3MDU5Cj4gKwkJCU1YNlFETF9QQURfU0QzX0RBVDdfX1NEM19EQVRBNwkJCTB4 MTcwNTkKPiArCQkJTVg2UURMX1BBRF9TRDNfUlNUX19TRDNfUkVTRVQJCQkweDFiMGIxCj4gKwkJ PjsKPiArCX07Cj4gKwo+ICsJcGluY3RybF91c2RoYzE6IHVzZGhjMWdycCB7Cj4gKwkJZnNsLHBp bnMgPSA8Cj4gKwkJCU1YNlFETF9QQURfU0QxX0NNRF9fU0QxX0NNRAkJCTB4MTcwNTkKPiArCQkJ TVg2UURMX1BBRF9TRDFfQ0xLX19TRDFfQ0xLCQkJMHgxMDA1OQo+ICsJCQlNWDZRRExfUEFEX1NE MV9EQVQwX19TRDFfREFUQTAJCQkweDE3MDU5Cj4gKwkJCU1YNlFETF9QQURfU0QxX0RBVDFfX1NE MV9EQVRBMQkJCTB4MTcwNTkKPiArCQkJTVg2UURMX1BBRF9TRDFfREFUMl9fU0QxX0RBVEEyCQkJ MHgxNzA1OQo+ICsJCQlNWDZRRExfUEFEX1NEMV9EQVQzX19TRDFfREFUQTMJCQkweDE3MDU5Cj4g KwkJCU1YNlFETF9QQURfR1BJT18xX19TRDFfQ0RfQgkJCTB4MWIwYjEKPiArCQkJTVg2UURMX1BB RF9ESTBfUElONF9fU0QxX1dQCQkJMHgxYjBiMQo+ICsJCT47Cj4gKwl9Owo+ICsKPiArCXBpbmN0 cmxfdXNkaGMyOiB1c2RoYzJncnAgewo+ICsJCWZzbCxwaW5zID0gPAo+ICsJCQlNWDZRRExfUEFE X1NEMl9DTURfX1NEMl9DTUQJCQkweDE3MDU5Cj4gKwkJCU1YNlFETF9QQURfU0QyX0NMS19fU0Qy X0NMSwkJCTB4MTAwNTkKPiArCQkJTVg2UURMX1BBRF9TRDJfREFUMF9fU0QyX0RBVEEwCQkJMHgx NzA1OQo+ICsJCQlNWDZRRExfUEFEX1NEMl9EQVQxX19TRDJfREFUQTEJCQkweDE3MDU5Cj4gKwkJ CU1YNlFETF9QQURfU0QyX0RBVDJfX1NEMl9EQVRBMgkJCTB4MTcwNTkKPiArCQkJTVg2UURMX1BB RF9TRDJfREFUM19fU0QyX0RBVEEzCQkJMHgxNzA1OQo+ICsJCQlNWDZRRExfUEFEX0dQSU9fNF9f U0QyX0NEX0IJCQkweDFiMGIxCj4gKwkJCU1YNlFETF9QQURfR1BJT18yX19TRDJfV1AJCQkweDFi MGIxCj4gKwkJPjsKPiArCX07Cj4gKwo+ICt9Owo+ICsKPiArCj4gKyZpMmMxIHsKPiArCWNsb2Nr LWZyZXF1ZW5jeSA9IDwxMDAwMDA+Owo+ICsJcGluY3RybC1uYW1lcyA9ICJkZWZhdWx0IjsKPiAr CXBpbmN0cmwtMCA9IDwmcGluY3RybF9pMmMxPjsKPiArCXN0YXR1cyA9ICJva2F5IjsKPiArCj4g KwlydGM6IHJ0Y0A2OCB7Cj4gKwkJY29tcGF0aWJsZSA9ICJkYWxsYXMsZHMxMzA3IjsKPiArCQly ZWcgPSA8MHg2OD47Cj4gKwl9Owo+ICsKPiArCWRhOTA2MzogcG1pY0A1OCB7Cj4gKwkJY29tcGF0 aWJsZSA9ICJkbGcsZGE5MDYzIjsKPiArCQlyZWcgPSA8MHg1OD47Cj4gKwkJcGluY3RybC1uYW1l cyA9ICJkZWZhdWx0IjsKPiArCQlwaW5jdHJsLTAgPSA8JnBpbmN0cmxfcG1pYz47Cj4gKwkJaW50 ZXJydXB0LXBhcmVudCA9IDwmZ3BpbzI+Owo+ICsJCWludGVycnVwdHMgPSA8OCBJUlFfVFlQRV9M RVZFTF9MT1c+Owo+ICsJCWludGVycnVwdC1jb250cm9sbGVyOwo+ICsKPiArCQlvbmtleSB7Cj4g KwkJCWNvbXBhdGlibGUgPSAiZGxnLGRhOTA2My1vbmtleSI7Cj4gKwkJCXdha2V1cC1zb3VyY2U7 Cj4gKwkJfTsKPiArCj4gKwkJd2R0IHsKCnMvd2R0L3dhdGNoZG9nCgo+ICsJCQljb21wYXRpYmxl ID0gImRsZyxkYTkwNjMtd2F0Y2hkb2ciOwo+ICsJCQl0aW1lb3V0LXNlYyA9IDwwPjsKPiArCQl9 Owo+ICsKPiArCQlyZWd1bGF0b3JzIHsKPiArCQkJdmRkY29yZV9yZWc6IGJjb3JlMSB7Cj4gKwkJ CQlyZWd1bGF0b3ItbWluLW1pY3Jvdm9sdCA9IDwxMTAwMDAwPjsKPiArCQkJCXJlZ3VsYXRvci1t YXgtbWljcm92b2x0ID0gPDE0NTAwMDA+Owo+ICsJCQkJcmVndWxhdG9yLXJhbXAtZGVsYXkgPSA8 MjAwMDA+Owo+ICsJCQkJcmVndWxhdG9yLW5hbWUgPSAiREE5MDYzX0NPUkUiOwo+ICsJCQkJcmVn dWxhdG9yLWFsd2F5cy1vbjsKPiArCQkJfTsKPiArCj4gKwkJCXZkZHNvY19yZWc6IGJjb3JlMiB7 Cj4gKwkJCQlyZWd1bGF0b3ItbWluLW1pY3Jvdm9sdCA9IDwxMTAwMDAwPjsKPiArCQkJCXJlZ3Vs YXRvci1tYXgtbWljcm92b2x0ID0gPDE0NTAwMDA+Owo+ICsJCQkJcmVndWxhdG9yLXJhbXAtZGVs YXkgPSA8MjAwMDA+Owo+ICsJCQkJcmVndWxhdG9yLW5hbWUgPSAiREE5MDYzX1NPQyI7Cj4gKwkJ CQlyZWd1bGF0b3ItYWx3YXlzLW9uOwo+ICsJCQl9Owo+ICsKPiArCQkJdmRkX2RkcjNfcmVnOiBi cHJvIHsKPiArCQkJCXJlZ3VsYXRvci1taW4tbWljcm92b2x0ID0gPDE1MDAwMDA+Owo+ICsJCQkJ cmVndWxhdG9yLW1heC1taWNyb3ZvbHQgPSA8MTUwMDAwMD47Cj4gKwkJCQlyZWd1bGF0b3ItcmFt cC1kZWxheSA9IDwyMDAwMD47Cj4gKwkJCQlyZWd1bGF0b3ItYWx3YXlzLW9uOwo+ICsJCQl9Owo+ ICsKPiArCQkJdmRkXzN2M19yZWc6IGJwZXJpIHsKPiArCQkJCXJlZ3VsYXRvci1taW4tbWljcm92 b2x0ID0gPDMzMDAwMDA+Owo+ICsJCQkJcmVndWxhdG9yLW1heC1taWNyb3ZvbHQgPSA8MzMwMDAw MD47Cj4gKwkJCQlyZWd1bGF0b3ItcmFtcC1kZWxheSA9IDwyMDAwMD47Cj4gKwkJCQlyZWd1bGF0 b3ItYWx3YXlzLW9uOwo+ICsJCQl9Owo+ICsKPiArCQkJdmRkX3NhdGFfcmVnOiBsZG8zIHsKPiAr CQkJCXJlZ3VsYXRvci1taW4tbWljcm92b2x0ID0gPDI1MDAwMDA+Owo+ICsJCQkJcmVndWxhdG9y LW1heC1taWNyb3ZvbHQgPSA8MjUwMDAwMD47Cj4gKwkJCQlyZWd1bGF0b3ItYWx3YXlzLW9uOwo+ ICsJCQl9Owo+ICsJCQl2ZGRfbWlwaV9yZWc6IGxkbzQgewo+ICsJCQkJcmVndWxhdG9yLW1pbi1t aWNyb3ZvbHQgPSA8MjUwMDAwMD47Cj4gKwkJCQlyZWd1bGF0b3ItbWF4LW1pY3Jvdm9sdCA9IDwy NTAwMDAwPjsKPiArCQkJCXJlZ3VsYXRvci1hbHdheXMtb247Cj4gKwkJCX07Cj4gKwo+ICsJCQl2 ZGRfbXg2X3NudnNfcmVnOiBsZG81IHsKPiArCQkJCXJlZ3VsYXRvci1taW4tbWljcm92b2x0ID0g PDMzMDAwMDA+Owo+ICsJCQkJcmVndWxhdG9yLW1heC1taWNyb3ZvbHQgPSA8MzMwMDAwMD47Cj4g KwkJCQlyZWd1bGF0b3ItYWx3YXlzLW9uOwo+ICsJCQl9Owo+ICsKPiArCQkJdmRkX2hkbWlfcmVn OiBsZG82IHsKPiArCQkJCXJlZ3VsYXRvci1taW4tbWljcm92b2x0ID0gPDI1MDAwMDA+Owo+ICsJ CQkJcmVndWxhdG9yLW1heC1taWNyb3ZvbHQgPSA8MjUwMDAwMD47Cj4gKwkJCQlyZWd1bGF0b3It YWx3YXlzLW9uOwo+ICsJCQkJcmVndWxhdG9yLWJvb3Qtb247Cj4gKwkJCX07Cj4gKwo+ICsJCQl2 ZGRfcGNpZV9yZWc6IGxkbzcgewo+ICsJCQkJcmVndWxhdG9yLW1pbi1taWNyb3ZvbHQgPSA8MjUw MDAwMD47Cj4gKwkJCQlyZWd1bGF0b3ItbWF4LW1pY3Jvdm9sdCA9IDwyNTAwMDAwPjsKPiArCQkJ CXJlZ3VsYXRvci1hbHdheXMtb247Cj4gKwkJCX07Cj4gKwo+ICsJCQl2ZGRfMVY4X3JlZzogbGRv OCB7Cj4gKwkJCQlyZWd1bGF0b3ItbWluLW1pY3Jvdm9sdCA9IDwxODAwMDAwPjsKPiArCQkJCXJl Z3VsYXRvci1tYXgtbWljcm92b2x0ID0gPDE4MDAwMDA+Owo+ICsJCQkJcmVndWxhdG9yLWFsd2F5 cy1vbjsKPiArCQkJfTsKPiArCj4gKwkJCXZkZF8zVjNfc2RjX3JlZzogbGRvOSB7Cj4gKwkJCQly ZWd1bGF0b3ItbWluLW1pY3Jvdm9sdCA9IDwxODAwMDAwPjsKPiArCQkJCXJlZ3VsYXRvci1tYXgt bWljcm92b2x0ID0gPDMzMDAwMDA+Owo+ICsJCQkJcmVndWxhdG9yLWFsd2F5cy1vbjsKPiArCQkJ fTsKPiArCj4gKwkJCXZkZF8xVjJfcmVnOiBsZG8xMCB7Cj4gKwkJCQlyZWd1bGF0b3ItbWluLW1p Y3Jvdm9sdCA9IDwxMjAwMDAwPjsKPiArCQkJCXJlZ3VsYXRvci1tYXgtbWljcm92b2x0ID0gPDEy MDAwMDA+Owo+ICsJCQkJcmVndWxhdG9yLWFsd2F5cy1vbjsKPiArCQkJfTsKPiArCQl9Owo+ICsJ fTsKPiArfTsKPiArCj4gKyZ1YXJ0MSB7Cj4gKwlwaW5jdHJsLW5hbWVzID0gImRlZmF1bHQiOwo+ ICsJcGluY3RybC0wID0gPCZwaW5jdHJsX3VhcnQxPjsKPiArCXN0YXR1cyA9ICJva2F5IjsKPiAr fTsKPiArCj4gKyZ1YXJ0MiB7Cj4gKwlwaW5jdHJsLW5hbWVzID0gImRlZmF1bHQiOwo+ICsJcGlu Y3RybC0wID0gPCZwaW5jdHJsX3VhcnQyPjsKPiArfTsKPiArCj4gKyZ1YXJ0MyB7Cj4gKwlwaW5j dHJsLW5hbWVzID0gImRlZmF1bHQiOwo+ICsJcGluY3RybC0wID0gPCZwaW5jdHJsX3VhcnQzPjsK PiArfTsKPiArCj4gKyZ1YXJ0NCB7Cj4gKwlwaW5jdHJsLW5hbWVzID0gImRlZmF1bHQiOwo+ICsJ cGluY3RybC0wID0gPCZwaW5jdHJsX3VhcnQ0PjsKPiArfTsKPiArCj4gKyZ1YXJ0NSB7Cj4gKwlw aW5jdHJsLW5hbWVzID0gImRlZmF1bHQiOwo+ICsJcGluY3RybC0wID0gPCZwaW5jdHJsX3VhcnQ1 PjsKPiArfTsKPiArCj4gKyZmZWMgewo+ICsJcGluY3RybC1uYW1lcyA9ICJkZWZhdWx0IjsKPiAr CXBpbmN0cmwtMCA9IDwmcGluY3RybF9lbmV0PjsKPiArCXBoeS1tb2RlID0gInJnbWlpIjsKPiAr CXBoeS1yZXNldC1ncGlvcyA9IDwmZ3BpbzUgMjAgR1BJT19BQ1RJVkVfTE9XPjsKPiArCXBoeS1y ZXNldC1kdXJhdGlvbiA9IDw1MD47Cj4gKwlwaHktc3VwcGx5ID0gPCZ2ZGRfMVY4X3JlZz47Cj4g KwlwaHktaGFuZGxlID0gPCZrc3o5MDMxPjsKPiArCXN0YXR1cyA9ICJva2F5IjsKPiArCj4gKwo+ ICsJbWRpbyB7Cj4gKwkJI2FkZHJlc3MtY2VsbHMgPSA8MT47Cj4gKwkJI3NpemUtY2VsbHMgPSA8 MD47Cj4gKwo+ICsJCWtzejkwMzE6IHBoeUAwIHsKPiArCQkJY29tcGF0aWJsZSA9ICJldGhlcm5l dC1waHktaWVlZTgwMi4zLWMyMiI7Cj4gKwkJCXJlZyA9IDwwPjsKPiArCQkJaW50ZXJydXB0LXBh cmVudCA9IDwmZ3BpbzE+Owo+ICsJCQlpbnRlcnJ1cHRzID0gPDMwIElSUV9UWVBFX0VER0VfRkFM TElORz47Cj4gKwkJCXJ4ZHYtc2tldy1wcyA9IDw0ODA+Owo+ICsJCQl0eGVuLXNrZXctcHMgPSA8 NDgwPjsKPiArCQkJcnhkMC1za2V3LXBzID0gPDQ4MD47Cj4gKwkJCXJ4ZDEtc2tldy1wcyA9IDw0 ODA+Owo+ICsJCQlyeGQyLXNrZXctcHMgPSA8NDgwPjsKPiArCQkJcnhkMy1za2V3LXBzID0gPDQ4 MD47Cj4gKwkJCXR4ZDAtc2tldy1wcyA9IDw0MjA+Owo+ICsJCQl0eGQxLXNrZXctcHMgPSA8NDIw PjsKPiArCQkJdHhkMi1za2V3LXBzID0gPDM2MD47Cj4gKwkJCXR4ZDMtc2tldy1wcyA9IDwzNjA+ Owo+ICsJCQl0eGMtc2tldy1wcyA9IDwxMDIwPjsKPiArCQkJcnhjLXNrZXctcHMgPSA8OTYwPjsK PiArCQl9Owo+ICsJfTsKPiArfTsKPiArCj4gKwo+ICsmdXNkaGMzIHsKPiArCXBpbmN0cmwtbmFt ZXMgPSAiZGVmYXVsdCI7Cj4gKwlwaW5jdHJsLTAgPSA8JnBpbmN0cmxfdXNkaGMzPjsKPiArCW5v bi1yZW1vdmFibGU7Cj4gKwlidXMtd2lkdGggPSA8OD47Cj4gKwlzdGF0dXMgPSAib2theSI7Cj4g K307Cj4gKwo+ICsmcGNpZSB7Cj4gKwlwaW5jdHJsLW5hbWVzID0gImRlZmF1bHQiOwo+ICsJcGlu Y3RybC0wID0gPCZwaW5jdHJsX3BjaWVfY3RybD47Cj4gKwlyZXNldC1ncGlvID0gPCZncGlvNyAx MiBHUElPX0FDVElWRV9MT1c+Owo+ICsJZGlzYWJsZS1ncGlvID0gPCZncGlvMiAyMiBHUElPX0FD VElWRV9MT1c+Owo+ICt9Owo+ICsKPiArJmkyYzIgewo+ICsJY2xvY2stZnJlcXVlbmN5ID0gPDEw MDAwMD47Cj4gKwlwaW5jdHJsLW5hbWVzID0gImRlZmF1bHQiOwo+ICsJcGluY3RybC0wID0gPCZw aW5jdHJsX2kyYzI+Owo+ICt9Owo+ICsKPiArJnVzZGhjMSB7Cj4gKwlwaW5jdHJsLW5hbWVzID0g ImRlZmF1bHQiOwo+ICsJcGluY3RybC0wID0gPCZwaW5jdHJsX3VzZGhjMT47Cj4gKwlmc2wsd3At Y29udHJvbGxlcjsKPiArfTsKPiArCj4gKyZ1c2RoYzIgewo+ICsJcGluY3RybC1uYW1lcyA9ICJk ZWZhdWx0IjsKPiArCXBpbmN0cmwtMCA9IDwmcGluY3RybF91c2RoYzI+Owo+ICsJZnNsLHdwLWNv bnRyb2xsZXI7Cj4gK307Cj4gKwo+ICsKPiArJmlwdTFfZGkwX2Rpc3AwIHsKPiArCXJlbW90ZS1l bmRwb2ludCA9IDwmcmdiX2VuY29kZXJfaW4+Owo+ICt9Owo+ICsKPiArJnB3bTEgewo+ICsJc3Rh dHVzID0gIm9rYXkiOwo+ICt9Owo+ICsKPiArJnB3bTMgewo+ICsJc3RhdHVzID0gIm9rYXkiOwo+ ICt9Owo+ICsKPiArJnB3bTQgewo+ICsJc3RhdHVzID0gIm9rYXkiOwo+ICt9Owo+ICsKPiArJmVj c3BpMiB7Cj4gKwlwaW5jdHJsLW5hbWVzID0gImRlZmF1bHQiOwo+ICsJcGluY3RybC0wID0gPCZw aW5jdHJsX2Vjc3BpMj47Cj4gKwljcy1ncGlvcyA9ICA8JmdwaW8yIDI1IEdQSU9fQUNUSVZFX0hJ R0g+LAo+ICsJCQkJPCZncGlvMiAyNiBHUElPX0FDVElWRV9ISUdIPjsKPiArfTsKPiArCj4gKyZl Y3NwaTQgewo+ICsJcGluY3RybC1uYW1lcyA9ICJkZWZhdWx0IjsKPiArCXBpbmN0cmwtMCA9IDwm cGluY3RybF9ub3JfZmxhc2g+Owo+ICt9Owo+ICsKPiArJmNhbjEgewo+ICsJcGluY3RybC1uYW1l cyA9ICJkZWZhdWx0IjsKPiArCXBpbmN0cmwtMCA9IDwmcGluY3RybF9jYW4xPjsKPiArfTsKPiAr Cj4gKyZjYW4yIHsKPiArCXBpbmN0cmwtbmFtZXMgPSAiZGVmYXVsdCI7Cj4gKwlwaW5jdHJsLTAg PSA8JnBpbmN0cmxfY2FuMj47Cj4gK307Cj4gKwo+ICsmdXNiaDEgewo+ICsJcGluY3RybC1uYW1l cyA9ICJkZWZhdWx0IjsKPiArCXBpbmN0cmwtMCA9IDwmcGluY3RybF91c2JfaG9zdDE+Owo+ICt9 Owo+ICsKPiArJnVzYm90ZyB7Cj4gKwlwaW5jdHJsLW5hbWVzID0gImRlZmF1bHQiOwo+ICsJcGlu Y3RybC0wID0gPCZwaW5jdHJsX3VzYl9vdGc+Owo+ICsJdmJ1cy1zdXBwbHkgPSA8JnJlZ191c2Jf b3RnPjsKPiArCWRyX21vZGUgPSAicGVyaXBoZXJhbCI7Cj4gK307Cj4gKwo+ICsvKioqKioqZGV2 aWNlIHBvd2VyIE1hbmFnZW1lbnQqKioqKioqKiovCj4gKwo+ICsmY3B1MCB7Cj4gKwl2b2x0YWdl LXRvbGVyYW5jZSA9IDwyPjsKPiArfTsKPiArCj4gKyZyZWdfYXJtIHsKPiArCXZpbi1zdXBwbHkg PSA8JnZkZGNvcmVfcmVnPjsKPiArfTsKPiArCj4gKyZyZWdfc29jIHsKPiArCXZpbi1zdXBwbHkg PSA8JnZkZHNvY19yZWc+Owo+ICt9Owo+ICsKPiArJnJlZ19wdSB7Cj4gKwl2aW4tc3VwcGx5ID0g PCZ2ZGRzb2NfcmVnPjsKPiArfTsKPiArCj4gKwo+ICsKPiArLyoqKioqKipEaXNhYmxlZCBIVyBm b2xsb3dpbmcqKioqKioqKioqKi8KPiArCj4gKwo+ICsmd2VpbSB7Cj4gKwlzdGF0dXMgPSAiZGlz YWJsZWQiOwo+ICt9OwoKSXNuJ3Qgd2VpbSBkaXNhYmxlZCBieSBkZWZhdWx0PwoKU2hhd24KCj4g Kwo+ICsmc252c19ydGMgewo+ICsJc3RhdHVzID0gImRpc2FibGVkIjsKPiArfTsKPiAtLSAKPiAy LjExLjAKPiAKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18K ZHJpLWRldmVsIG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0 dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754290AbeDWIpy (ORCPT ); Mon, 23 Apr 2018 04:45:54 -0400 Received: from mail.kernel.org ([198.145.29.99]:56828 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753109AbeDWIpt (ORCPT ); Mon, 23 Apr 2018 04:45:49 -0400 DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C0E0C21759 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=shawnguo@kernel.org Date: Mon, 23 Apr 2018 16:44:56 +0800 From: Shawn Guo To: jan.tuerk@emtrion.com Cc: Rob Herring , Mark Rutland , Thierry Reding , David Airlie , Sascha Hauer , Fabio Estevam , Russell King , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v3 5/6] ARM: dts: Add support for emtrion emCON-MX6 series Message-ID: <20180423084454.GZ25429@dragon> References: <20171220134710.64479-2-jan.tuerk@emtrion.com> <20180420125108.14197-1-jan.tuerk@emtrion.com> <20180420125108.14197-6-jan.tuerk@emtrion.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20180420125108.14197-6-jan.tuerk@emtrion.com> User-Agent: Mutt/1.5.21 (2010-09-15) Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Apr 20, 2018 at 02:50:52PM +0200, jan.tuerk@emtrion.com wrote: > From: Jan Tuerk > > This patch adds support for the emtrion GmbH emCON-MX6 modules. > They are available with imx.6 Solo, Dual-Lite, Dual and Quad > equipped with Memory from 512MB to 2GB (configured by U-Boot). > > Our default developer-Kit ships with the Avari baseboard and the > EDT ETM0700G0BDH6 Display (imx6[q|dl]-emcon-avari). > > The devicetree is split into the common part providing all module > components and the basic support for all SoC versions > (imx6qdl-emcon.dtsi) and parts which are i.mx6 S|DL and D|Q relevant. > Finally the support for the avari baseboard in the developer-kit > configuration is provided by the emcon-avari dts files. > > Signed-off-by: Jan Tuerk > --- > Documentation/devicetree/bindings/arm/emtrion.txt | 13 + It's better to have a separate patch for bindings doc, which needs to be acknowledged by DT maintainers. > arch/arm/boot/dts/Makefile | 2 + > arch/arm/boot/dts/imx6dl-emcon-avari.dts | 224 ++++++ > arch/arm/boot/dts/imx6dl-emcon.dtsi | 27 + > arch/arm/boot/dts/imx6q-emcon-avari.dts | 224 ++++++ > arch/arm/boot/dts/imx6q-emcon.dtsi | 27 + > arch/arm/boot/dts/imx6qdl-emcon.dtsi | 838 ++++++++++++++++++++++ > 7 files changed, 1355 insertions(+) > create mode 100644 Documentation/devicetree/bindings/arm/emtrion.txt > create mode 100644 arch/arm/boot/dts/imx6dl-emcon-avari.dts > create mode 100644 arch/arm/boot/dts/imx6dl-emcon.dtsi > create mode 100644 arch/arm/boot/dts/imx6q-emcon-avari.dts > create mode 100644 arch/arm/boot/dts/imx6q-emcon.dtsi > create mode 100644 arch/arm/boot/dts/imx6qdl-emcon.dtsi > > diff --git a/Documentation/devicetree/bindings/arm/emtrion.txt b/Documentation/devicetree/bindings/arm/emtrion.txt > new file mode 100644 > index 000000000000..3ff6c6c2034d > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/emtrion.txt > @@ -0,0 +1,13 @@ > +Emtrion Devicetree Bindings > +=========================== > + > +emCON Series: > +------------- > + > +Required root node properties > + - compatible: > + - "emtrion,emcon-mx6", "fsl,imx6q", "fsl,imx6dl"; : emCON-MX6 Generic SoM > + - "emtrion,emcon-mx6", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM > + - "emtrion,emcon-mx6-avari", "fsl,imx6q"; : emCON-MX6D or emCON-MX6Q SoM on Avari Base > + - "emtrion,emcon-mx6", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM > + - "emtrion,emcon-mx6-avari", "fsl,imx6dl"; : emCON-MX6S or emCON-MX6DL SoM on Avari Base > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile > index 7e2424957809..05b930da3fda 100644 > --- a/arch/arm/boot/dts/Makefile > +++ b/arch/arm/boot/dts/Makefile > @@ -381,6 +381,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ > imx6dl-cubox-i-emmc-som-v15.dtb \ > imx6dl-cubox-i-som-v15.dtb \ > imx6dl-dfi-fs700-m60.dtb \ > + imx6dl-emcon-avari.dtb \ > imx6dl-gw51xx.dtb \ > imx6dl-gw52xx.dtb \ > imx6dl-gw53xx.dtb \ > @@ -442,6 +443,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ > imx6q-display5-tianma-tm070-1280x768.dtb \ > imx6q-dmo-edmqmx6.dtb \ > imx6q-dms-ba16.dtb \ > + imx6q-emcon-avari.dtb \ > imx6q-evi.dtb \ > imx6q-gk802.dtb \ > imx6q-gw51xx.dtb \ > diff --git a/arch/arm/boot/dts/imx6dl-emcon-avari.dts b/arch/arm/boot/dts/imx6dl-emcon-avari.dts > new file mode 100644 > index 000000000000..2344fb9498e3 > --- /dev/null > +++ b/arch/arm/boot/dts/imx6dl-emcon-avari.dts > @@ -0,0 +1,224 @@ > +// SPDX-License-Identifier: (GPL-2.0 or MIT) > +/* Copyright (C) 2018 emtrion GmbH > + * Author: Jan Tuerk > + */ /* * Copyright ... */ > + > +/dts-v1/; > +#include "imx6dl.dtsi" > +#include "imx6qdl-emcon.dtsi" > +#include "imx6dl-emcon.dtsi" /*Include camera2 pinmux*/ /* bla bla */ > + > +/ { > + model = "emtrion SoM emCON-MX6 Solo/Dual-Lite Avari"; > + compatible = "emtrion,emcon-mx6-avari", "fsl,imx6dl"; > + > + aliases { > + mmc0 = &usdhc3; > + mmc2 = &usdhc1; > + mmc1 = &usdhc2; > + mmc3 = &usdhc4; > + }; > + > + chosen { > + stdout-path = <&uart1>; > + }; > + > + memory { The unit-address is missing. > + reg = <0x10000000 0x40000000>; > + }; > + > + supplies { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <0>; DT maintainers do not like this fake container node. Please put the fixed regulator nodes directly under root with a unique name like below. reg_xxx: regulator-xxx { ... }; > + > + wallplug5p0: supply@0 { > + compatible = "regulator-fixed"; > + reg = <0>; > + regulator-name = "WALL-PLUG"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + regulator-always-on; > + regulator-boot-on; > + }; > + > + base3p3: supply@1 { > + compatible = "regulator-fixed"; > + reg = <1>; > + vin-supply = <&wallplug5p0>; > + regulator-name = "3V3-avari"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-always-on; > + regulator-boot-on; > + }; > + > + base1p5: supply@2 { > + compatible = "regulator-fixed"; > + reg = <2>; > + vin-supply = <&base3p3>; > + regulator-name = "1V5-avari"; > + regulator-min-microvolt = <1500000>; > + regulator-max-microvolt = <1500000>; > + regulator-always-on; > + regulator-boot-on; > + }; > + > + reg_usb_otg: otgvbus@3 { > + compatible = "regulator-fixed"; > + reg = <3>; > + vin-supply = <&wallplug5p0>; > + regulator-name = "OTG_VBUS"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; > + regulator-always-on; > + }; > + > + }; > + > + > + sndosc: 12MHZosc { clock-xxx { ... }; > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <12000000>; > + }; > + > + sound { > + compatible = "fsl,imx-audio-sgtl5000"; > + model = "emCON-avari-sgtl5000"; > + ssi-controller = <&ssi2>; > + audio-codec = <&sgtl5000>; > + audio-routing = > + "Headphone Jack", "HP_OUT"; > + mux-int-port = <2>; > + mux-ext-port = <3>; > + }; > + > +}; > + > + One newline is good enough. > +&iomuxc { > + pinctrl-names = "default"; > + /*Unused emCON-MX6 outputs on AVARI*/ > + pinctrl-0 = < > + &pinctrl_emcon_gpio1 &pinctrl_emcon_gpio2 > + &pinctrl_emcon_gpio3 &pinctrl_emcon_gpio5 > + &pinctrl_emcon_gpio6 &pinctrl_emcon_gpio7 > + &pinctrl_emcon_gpio8 &pinctrl_emcon_irq_a > + &pinctrl_emcon_irq_b &pinctrl_emcon_irq_c > + &pinctrl_emcon_irq_pwr &pinctrl_nor_flash > + &pinctrl_usdhc2 > + &pinctrl_spdif_out &pinctrl_spdif_in > + &pinctrl_cpi1 &pinctrl_cpi2 > + >; Only pins without clear consumer should be put into hog group. Also the indent seems broken. > +}; > + > +&audmux { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_audmux>; > + status = "okay"; > +}; > + > + > + One newline is good enough. Also, please try to sort these labelled nodes alphabetically. > +&i2c3 { > + clock-frequency = <100000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c3>; > + status = "okay"; > + > + sgtl5000: audio-codec@a { > + compatible = "fsl,sgtl5000"; > + reg = <0x0a>; > + clocks = <&sndosc>; > + VDDA-supply = <&base3p3>; > + VDDIO-supply = <&base3p3>; #sound-dai-cells is missing. > + }; > + > + boardID: pca8754a@3a { Please find a more generic node name for it. > + compatible = "nxp,pca8574"; > + reg = <0x3a>; > + gpio-controller; > + #gpio-cells = <1>; > + }; > + > + captouch: touchscreen@38 { > + compatible = "edt,edt-ft5406"; > + reg = <0x38>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_irq_touch2 &pinctrl_emcon_gpio4>; > + interrupt-parent = <&gpio6>; > + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; > + wake-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; > + wakeup-source; > + status = "okay"; The "okay" status is only needed to flip the default "disabled" device. > + }; > +}; > + > +&ssi2 { > + status = "okay"; > +}; > + > +&rgb_encoder { > + status = "okay"; > +}; > + > +&rgb_panel { > + compatible = "edt,etm0700g0bdh6"; > + status = "okay"; > +}; > + > +&i2c2 { > + status = "okay"; > +}; > + > +&hdmi { > + ddc-i2c-bus = <&i2c2>; > + status = "okay"; > +}; > + > +&usbh1 { > + status = "okay"; > +}; > + > +&usbotg { > + status = "okay"; > +}; > + > +&pcie { > + status = "okay"; > +}; > + > +&usdhc1 { > + status = "okay"; > +}; > + > +&can1 { > + status = "okay"; > +}; > + > +&can2 { > + status = "okay"; > +}; > + > +&uart2 { > + status = "okay"; > + uart-has-rtscts; > +}; > + > +&uart3 { > + status = "okay"; > +}; > + > +&uart4 { > + status = "okay"; > +}; > + > +&uart5 { > + status = "okay"; > +}; > + > +&ecspi2 { > + status = "okay"; > +}; > diff --git a/arch/arm/boot/dts/imx6dl-emcon.dtsi b/arch/arm/boot/dts/imx6dl-emcon.dtsi > new file mode 100644 > index 000000000000..1ed629c9747e > --- /dev/null > +++ b/arch/arm/boot/dts/imx6dl-emcon.dtsi > @@ -0,0 +1,27 @@ > +// SPDX-License-Identifier: (GPL-2.0 or MIT) > +/* Copyright (C) 2018 emtrion GmbH > + * Author: Jan Tuerk > + */ > + > +/ { > + model = "emtrion SoM emCON-MX6 Solo/DualLite"; > + compatible = "emtrion,emcon-mx6", "fsl,imx6dl"; > +}; > + > +&iomuxc { > + pinctrl_cpi2: csi1grp { > + fsl,pins = < > + MX6QDL_PAD_EIM_D17__IPU1_CSI1_PIXCLK 0x0b0b1 > + MX6QDL_PAD_EIM_EB3__IPU1_CSI1_HSYNC 0x1b0b1 > + MX6QDL_PAD_EIM_D29__IPU1_CSI1_VSYNC 0x1b0b1 > + MX6QDL_PAD_EIM_A17__IPU1_CSI1_DATA12 0x1b0b1 > + MX6QDL_PAD_EIM_D27__IPU1_CSI1_DATA13 0x1b0b1 > + MX6QDL_PAD_EIM_D26__IPU1_CSI1_DATA14 0x1b0b1 > + MX6QDL_PAD_EIM_D20__IPU1_CSI1_DATA15 0x1b0b1 > + MX6QDL_PAD_EIM_D19__IPU1_CSI1_DATA16 0x1b0b1 > + MX6QDL_PAD_EIM_D18__IPU1_CSI1_DATA17 0x1b0b1 > + MX6QDL_PAD_EIM_D16__IPU1_CSI1_DATA18 0x1b0b1 > + MX6QDL_PAD_EIM_EB2__IPU1_CSI1_DATA19 0x1b0b1 > + >; > + }; > +}; > diff --git a/arch/arm/boot/dts/imx6q-emcon-avari.dts b/arch/arm/boot/dts/imx6q-emcon-avari.dts > new file mode 100644 > index 000000000000..0c85b5ee011c > --- /dev/null > +++ b/arch/arm/boot/dts/imx6q-emcon-avari.dts There are so many things duplicated between imx6dl-emcon-avari.dts and imx6q-emcon-avari.dts. Can you do something to avoid that? > @@ -0,0 +1,224 @@ > +// SPDX-License-Identifier: (GPL-2.0 or MIT) > +/* Copyright (C) 2018 emtrion GmbH > + * Author: Jan Tuerk > + */ > + > +/dts-v1/; > +#include "imx6q.dtsi" > +#include "imx6qdl-emcon.dtsi" > +#include "imx6q-emcon.dtsi" /*Include camera2 pinmux*/ > + > +/ { > + model = "emtrion SoM emCON-MX6 Dual/Quad on Avari"; > + compatible = "emtrion,emcon-mx6-avari", "fsl,imx6q"; > + > + aliases { > + mmc0 = &usdhc3; > + mmc2 = &usdhc1; > + mmc1 = &usdhc2; > + mmc3 = &usdhc4; > + }; > + > + chosen { > + stdout-path = <&uart1>; > + }; > + > + memory { > + reg = <0x10000000 0x40000000>; > + }; > + > + supplies { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <0>; > + > + wallplug5p0: supply@0 { > + compatible = "regulator-fixed"; > + reg = <0>; > + regulator-name = "WALL-PLUG"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + regulator-always-on; > + regulator-boot-on; > + }; > + > + base3p3: supply@1 { > + compatible = "regulator-fixed"; > + reg = <1>; > + vin-supply = <&wallplug5p0>; > + regulator-name = "3V3-avari"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-always-on; > + regulator-boot-on; > + }; > + > + base1p5: supply@2 { > + compatible = "regulator-fixed"; > + reg = <2>; > + vin-supply = <&base3p3>; > + regulator-name = "1V5-avari"; > + regulator-min-microvolt = <1500000>; > + regulator-max-microvolt = <1500000>; > + regulator-always-on; > + regulator-boot-on; > + }; > + > + reg_usb_otg: otgvbus@3 { > + compatible = "regulator-fixed"; > + reg = <3>; > + vin-supply = <&wallplug5p0>; > + regulator-name = "OTG_VBUS"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + gpio = <&gpio1 8 GPIO_ACTIVE_LOW>; > + regulator-always-on; > + }; > + > + }; > + > + > + sndosc: 12MHZosc { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <12000000>; > + }; > + > + sound { > + compatible = "fsl,imx-audio-sgtl5000"; > + model = "emCON-avari-sgtl5000"; > + ssi-controller = <&ssi2>; > + audio-codec = <&sgtl5000>; > + audio-routing = > + "Headphone Jack", "HP_OUT"; > + mux-int-port = <2>; > + mux-ext-port = <3>; > + }; > + > +}; > + > + > +&iomuxc { > + pinctrl-names = "default"; > + /*Unused emCON-MX6 pingroups on AVARI baseboard, enable defaults*/ > + pinctrl-0 = < > + &pinctrl_emcon_gpio1 &pinctrl_emcon_gpio2 > + &pinctrl_emcon_gpio3 &pinctrl_emcon_gpio5 > + &pinctrl_emcon_gpio6 &pinctrl_emcon_gpio7 > + &pinctrl_emcon_gpio8 &pinctrl_emcon_irq_a > + &pinctrl_emcon_irq_b &pinctrl_emcon_irq_c > + &pinctrl_emcon_irq_pwr &pinctrl_nor_flash > + &pinctrl_usdhc2 > + &pinctrl_spdif_out &pinctrl_spdif_in > + &pinctrl_cpi1 &pinctrl_cpi2 > + >; > +}; > + > +&audmux { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_audmux>; > + status = "okay"; > +}; > + > + > + > +&i2c3 { > + clock-frequency = <100000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c3>; > + status = "okay"; > + > + sgtl5000: audio-codec@a { > + compatible = "fsl,sgtl5000"; > + reg = <0x0a>; > + clocks = <&sndosc>; > + VDDA-supply = <&base3p3>; > + VDDIO-supply = <&base3p3>; > + }; > + > + boardID: pca8754a@3a { > + compatible = "nxp,pca8574"; > + reg = <0x3a>; > + gpio-controller; > + #gpio-cells = <1>; > + }; > + > + captouch: touchscreen@38 { > + compatible = "edt,edt-ft5406"; > + reg = <0x38>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_irq_touch2 &pinctrl_emcon_gpio4>; > + interrupt-parent = <&gpio6>; > + interrupts = <31 IRQ_TYPE_EDGE_FALLING>; > + wake-gpios = <&gpio2 3 GPIO_ACTIVE_HIGH>; > + wakeup-source; > + status = "okay"; > + }; > +}; > + > +&ssi2 { > + status = "okay"; > +}; > + > +&rgb_encoder { > + status = "okay"; > +}; > + > +&rgb_panel { > + compatible = "edt,etm0700g0bdh6"; > + status = "okay"; > +}; > + > +&i2c2 { > + status = "okay"; > +}; > + > +&hdmi { > + ddc-i2c-bus = <&i2c2>; > + status = "okay"; > +}; > + > +&usbh1 { > + status = "okay"; > +}; > + > +&usbotg { > + status = "okay"; > +}; > + > +&pcie { > + status = "okay"; > +}; > + > +&usdhc1 { > + status = "okay"; > +}; > + > +&can1 { > + status = "okay"; > +}; > + > +&can2 { > + status = "okay"; > +}; > + > +&uart2 { > + status = "okay"; > + uart-has-rtscts; > +}; > + > +&uart3 { > + status = "okay"; > +}; > + > +&uart4 { > + status = "okay"; > +}; > + > +&uart5 { > + status = "okay"; > +}; > + > +&ecspi2 { > + status = "okay"; > +}; > diff --git a/arch/arm/boot/dts/imx6q-emcon.dtsi b/arch/arm/boot/dts/imx6q-emcon.dtsi > new file mode 100644 > index 000000000000..33b3fbf3fba0 > --- /dev/null > +++ b/arch/arm/boot/dts/imx6q-emcon.dtsi > @@ -0,0 +1,27 @@ > +// SPDX-License-Identifier: (GPL-2.0 or MIT) > +/* Copyright (C) 2018 emtrion GmbH > + * Author: Jan Tuerk > + */ > + > +/ { > + model = "emtrion SoM emCON-MX6 Dual/Quad"; > + compatible = "emtrion,emcon-mx6", "fsl,imx6q"; > +}; > + > +&iomuxc { > + pinctrl_cpi2: csi1grp { > + fsl,pins = < > + MX6QDL_PAD_EIM_D17__IPU2_CSI1_PIXCLK 0x0b0b1 > + MX6QDL_PAD_EIM_EB3__IPU2_CSI1_HSYNC 0x1b0b1 > + MX6QDL_PAD_EIM_D29__IPU2_CSI1_VSYNC 0x1b0b1 > + MX6QDL_PAD_EIM_A17__IPU2_CSI1_DATA12 0x1b0b1 > + MX6QDL_PAD_EIM_D27__IPU2_CSI1_DATA13 0x1b0b1 > + MX6QDL_PAD_EIM_D26__IPU2_CSI1_DATA14 0x1b0b1 > + MX6QDL_PAD_EIM_D20__IPU2_CSI1_DATA15 0x1b0b1 > + MX6QDL_PAD_EIM_D19__IPU2_CSI1_DATA16 0x1b0b1 > + MX6QDL_PAD_EIM_D18__IPU2_CSI1_DATA17 0x1b0b1 > + MX6QDL_PAD_EIM_D16__IPU2_CSI1_DATA18 0x1b0b1 > + MX6QDL_PAD_EIM_EB2__IPU2_CSI1_DATA19 0x1b0b1 > + >; > + }; > +}; > diff --git a/arch/arm/boot/dts/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/imx6qdl-emcon.dtsi > new file mode 100644 > index 000000000000..5f9296dce130 > --- /dev/null > +++ b/arch/arm/boot/dts/imx6qdl-emcon.dtsi > @@ -0,0 +1,838 @@ > +// SPDX-License-Identifier: (GPL-2.0 or MIT) > +/* Copyright (C) 2018 emtrion GmbH > + * Author: Jan Tuerk > + */ > + > +#include > +#include > +#include > + > +/ { > + > + model = "emtrion SoM emCON-MX6"; > + compatible = "emtrion,emcon-mx6", "fsl,imx6q", "fsl,imx6dl"; > + > + aliases { > + mmc0 = &usdhc3; > + mmc2 = &usdhc1; > + mmc1 = &usdhc2; > + }; > + > + regulators { > + compatible = "simple-bus"; > + #address-cells = <1>; > + #size-cells = <0>; > + > + reg_parallel_disp: regulator@0 { > + compatible = "regulator-fixed"; > + reg = <0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_rgb_bl_en>; > + regulator-name = "LCD-Supply"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + gpio = <&gpio7 9 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + }; > + > + reg_lvds_disp: regulator@1 { > + compatible = "regulator-fixed"; > + reg = <1>; > + regulator-name = "LVDS-Supply"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + gpio = <&gpio7 10 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + }; > + }; > + > + som_leds: leds { > + compatible = "gpio-leds"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_som_leds>; > + > + green { > + label = "som:green"; > + gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; > + linux,default-trigger = "heartbeat"; > + default-state = "on"; > + }; > + > + red { > + label = "som:red"; > + gpios = <&gpio3 1 GPIO_ACTIVE_LOW>; > + default-state = "keep"; > + }; > + > + }; > + > + gpio-keys { > + compatible = "gpio-keys"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_emcon_wake>; > + > + wake { > + label = "Wake"; > + linux,code = ; > + gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; > + wakeup-source; > + }; > + }; > + > + pwm_fan: pwm-fan { > + compatible = "pwm-fan"; > + cooling-min-state = <0>; > + cooling-max-state = <4>; > + #cooling-cells = <2>; > + pwms = <&pwm4 0 50000>; > + cooling-levels = <0 64 127 191 255>; > + status = "disabled"; > + }; > + > + rgb_encoder: disp0 { s/disp0/display > + compatible = "fsl,imx-parallel-display"; > + #address-cells = <1>; > + #size-cells = <0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_rgb24_display>; > + status = "disabled"; > + > + port@0 { > + reg = <0>; Have a newline between property list and child node. > + rgb_encoder_in: endpoint { > + remote-endpoint = <&ipu1_di0_disp0>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + rgb_encoder_out: endpoint { > + remote-endpoint = <&rgb_panel_in>; > + }; > + }; > + }; > + > + rgb_panel: panel { > + backlight = <&rgb_backlight>; > + power-supply = <®_parallel_disp>; > + port { > + rgb_panel_in: endpoint { > + remote-endpoint = <&rgb_encoder_out>; > + }; > + }; > + }; > + > + rgb_backlight: rgb-backlight { > + compatible = "pwm-backlight"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_rgb_bl>; > + enable-gpios = <&gpio6 8 GPIO_ACTIVE_HIGH>; > + pwms = <&pwm3 0 5000000>; > + brightness-levels = <250 176 160 144 128 112 > + 96 80 64 48 32 16 8 1 > + >; Broken indent. > + default-brightness-level = <13>; > + status = "okay"; > + }; > + > + lvds_backlight: lvds-backlight { > + compatible = "pwm-backlight"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_lvds_bl>; > + enable-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; > + pwms = <&pwm1 0 50000>; > + brightness-levels = <0 4 8 16 32 64 80 96 112 > + 128 144 160 176 250 > + >; > + default-brightness-level = <13>; > + status = "okay"; > + }; > +}; > + > + > +&iomuxc { > + > + pinctrl_secure: securegrp { Unused? > + fsl,pins = < > + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1 > + >; > + }; > + > + pinctrl_uart1: uart1grp { > + fsl,pins = < > + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 > + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 > + >; > + }; > + > + pinctrl_uart2: uart2grp { > + fsl,pins = < > + MX6QDL_PAD_SD4_DAT5__UART2_RTS_B 0x1b0b1 > + MX6QDL_PAD_SD4_DAT6__UART2_CTS_B 0x1b0b1 > + MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 > + MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 > + >; > + }; > + > + pinctrl_uart3: uart3grp { > + fsl,pins = < > + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 > + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 > + >; > + }; > + > + pinctrl_uart4: uart4grp { > + fsl,pins = < > + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 > + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 > + >; > + }; > + > + pinctrl_uart5: uart5grp { > + fsl,pins = < > + MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 > + MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 > + >; > + }; > + > + pinctrl_emcon_gpio1: emcongpio1 { > + fsl,pins = < > + MX6QDL_PAD_NANDF_D0__GPIO2_IO00 0x0b0b1 > + >; > + }; Try to keep these pinctrl entries alphabetically sorted. > + > + pinctrl_emcon_gpio2: emcongpio2 { > + fsl,pins = < > + MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x0b0b1 > + >; > + }; > + > + pinctrl_emcon_gpio3: emcongpio3 { > + fsl,pins = < > + MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x0b0b1 > + >; > + }; > + > + pinctrl_emcon_gpio4: emcongpio4 { > + fsl,pins = < > + MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x0b0b1 > + >; > + }; > + > + pinctrl_emcon_gpio5: emcongpio5 { > + fsl,pins = < > + MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x0b0b1 > + >; > + }; > + > + pinctrl_emcon_gpio6: emcongpio6 { > + fsl,pins = < > + MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x0b0b1 > + >; > + }; > + > + pinctrl_emcon_gpio7: emcongpio7 { > + fsl,pins = < > + MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x0b0b1 > + >; > + }; > + > + pinctrl_emcon_gpio8: emcongpio8 { > + fsl,pins = < > + MX6QDL_PAD_NANDF_D7__GPIO2_IO07 0x0b0b1 > + >; > + }; > + > + pinctrl_emcon_irq_a: emconirqa { > + fsl,pins = < > + MX6QDL_PAD_NANDF_CLE__GPIO6_IO07 0x0b0b1 > + >; > + }; > + > + pinctrl_emcon_irq_b: emconirqb { > + fsl,pins = < > + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x0b0b1 > + >; > + }; > + > + pinctrl_emcon_irq_c: emconirqc { > + fsl,pins = < > + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x0b0b1 > + >; > + }; > + > + pinctrl_emcon_wake: emconwake { > + fsl,pins = < > + MX6QDL_PAD_EIM_DA2__GPIO3_IO02 0x1b0b1 > + >; > + }; > + > + pinctrl_emcon_irq_pwr: emconirqpwr { > + fsl,pins = < > + MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x0b0b1 > + >; > + }; > + > + pinctrl_som_leds: somledgrp { > + fsl,pins = < > + MX6QDL_PAD_EIM_DA0__GPIO3_IO00 0x0b0b1 > + MX6QDL_PAD_EIM_DA1__GPIO3_IO01 0x0b0b1 > + >; > + }; > + > + pinctrl_nor_flash: norflashgrp { > + fsl,pins = < > + MX6QDL_PAD_NANDF_CS0__GPIO6_IO11 0x1b0b1 > + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 > + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 > + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 > + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 > + >; > + }; > + > + pinctrl_ecspi2: ecspi2grp { > + fsl,pins = < > + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 > + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 > + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 > + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1 > + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 > + >; > + }; > + > + pinctrl_pwm_fan: pwmfan { > + fsl,pins = < > + MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x0b0b1 > + >; > + }; > + > + pinctrl_can1: can1grp { > + fsl,pins = < > + MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 > + MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 > + >; > + }; > + > + pinctrl_can2: can2grp { > + fsl,pins = < > + MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x1b0b1 > + MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x1b0b1 > + >; > + }; > + > + pinctrl_spdif_out: spdifout { > + fsl,pins = < > + MX6QDL_PAD_GPIO_19__SPDIF_OUT 0x13091 > + >; > + }; > + > + pinctrl_spdif_in: spdifin { > + fsl,pins = < > + MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0 > + >; > + }; > + > + pinctrl_cpi1: csi0grp { > + fsl,pins = < > + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0xb0b1 > + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b1 > + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b1 > + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b1 > + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b1 > + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b1 > + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b1 > + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b1 > + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b1 > + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b1 > + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b1 > + >; > + }; > + > + /*camera2-pinctrl is in imx6q-emcon.dtsi or imx6dl-emcon.dtsi*/ > + > + pinctrl_pcie_ctrl: pciegrp { > + fsl,pins = < > + MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x1b0b1 > + MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x1b0b1 > + >; > + }; > + > + pinctrl_audmux: audmux { > + fsl,pins = < > + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x130b0 > + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b060 > + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x130B0 > + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b060 > + >; > + }; > + > + pinctrl_i2c1: i2c1grp { > + fsl,pins = < > + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 > + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 > + >; > + }; > + > + pinctrl_i2c2: i2c2grp { > + fsl,pins = < > + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 > + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 > + >; > + }; > + > + pinctrl_i2c3: i2c3grp { > + fsl,pins = < > + MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4000b070 > + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b870 > + >; > + }; > + > + pinctrl_pmic: pmicgrp { > + fsl,pins = < > + MX6QDL_PAD_SD4_DAT0__GPIO2_IO08 0x0b0b1 > + >; > + }; > + > + pinctrl_usb_host1: usbhgrp { > + fsl,pins = < > + MX6QDL_PAD_EIM_D31__USB_H1_PWR 0x1B058 > + MX6QDL_PAD_EIM_D30__USB_H1_OC 0x1B058 > + >; > + }; > + > + pinctrl_usb_otg: usbotggrp { > + fsl,pins = < > + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 > + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x17059 > + MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x17059 > + >; > + }; > + > + pinctrl_lvds_reg: lvdsreggrp { > + fsl,pins = < > + MX6QDL_PAD_SD4_CLK__GPIO7_IO10 0x0b0b1 > + >; > + }; > + > + pinctrl_lvds_bl: lvdsbacklightgrp { > + fsl,pins = < > + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x0b0b1 > + MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b1 > + >; > + }; > + > + pinctrl_irq_touch1: irqtouch1 { > + fsl,pins = < > + MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x0b0b1 > + >; > + }; > + > + pinctrl_rgb_bl_en: rgbenable { > + fsl,pins = < > + MX6QDL_PAD_SD4_CMD__GPIO7_IO09 0x0b0b1 > + >; > + }; > + > + pinctrl_irq_touch2: irqtouch2 { > + fsl,pins = < > + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x0b0b1 > + >; > + }; > + > + pinctrl_rgb_bl: rgbbacklightgrp { > + fsl,pins = < > + MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x0b0b1 > + MX6QDL_PAD_NANDF_ALE__GPIO6_IO08 0x0b0b1 > + >; > + }; > + > + pinctrl_rgb24_display: rgbgrp { > + fsl,pins = < > + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10 > + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10 > + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 > + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 > + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10 > + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10 > + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10 > + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10 > + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10 > + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10 > + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10 > + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10 > + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10 > + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10 > + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10 > + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10 > + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10 > + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10 > + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10 > + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10 > + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10 > + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10 > + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10 > + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10 > + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10 > + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10 > + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10 > + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10 > + >; > + }; > + > + pinctrl_enet: enetgrp { > + fsl,pins = < > + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b030 > + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b030 > + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 > + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 > + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 > + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 > + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 > + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 > + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x4001a0b1 > + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 > + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 > + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 > + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 > + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 > + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 > + MX6QDL_PAD_CSI0_DATA_EN__GPIO5_IO20 0x1b058 > + MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 > + >; > + }; > + > + > + pinctrl_usdhc3: usdhc3grp { > + fsl,pins = < > + MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 > + MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 > + MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 > + MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 > + MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 > + MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 > + MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 > + MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 > + MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 > + MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 > + MX6QDL_PAD_SD3_RST__SD3_RESET 0x1b0b1 > + >; > + }; > + > + pinctrl_usdhc1: usdhc1grp { > + fsl,pins = < > + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 > + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 > + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 > + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 > + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 > + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 > + MX6QDL_PAD_GPIO_1__SD1_CD_B 0x1b0b1 > + MX6QDL_PAD_DI0_PIN4__SD1_WP 0x1b0b1 > + >; > + }; > + > + pinctrl_usdhc2: usdhc2grp { > + fsl,pins = < > + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 > + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 > + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 > + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 > + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 > + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 > + MX6QDL_PAD_GPIO_4__SD2_CD_B 0x1b0b1 > + MX6QDL_PAD_GPIO_2__SD2_WP 0x1b0b1 > + >; > + }; > + > +}; > + > + > +&i2c1 { > + clock-frequency = <100000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c1>; > + status = "okay"; > + > + rtc: rtc@68 { > + compatible = "dallas,ds1307"; > + reg = <0x68>; > + }; > + > + da9063: pmic@58 { > + compatible = "dlg,da9063"; > + reg = <0x58>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pmic>; > + interrupt-parent = <&gpio2>; > + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; > + interrupt-controller; > + > + onkey { > + compatible = "dlg,da9063-onkey"; > + wakeup-source; > + }; > + > + wdt { s/wdt/watchdog > + compatible = "dlg,da9063-watchdog"; > + timeout-sec = <0>; > + }; > + > + regulators { > + vddcore_reg: bcore1 { > + regulator-min-microvolt = <1100000>; > + regulator-max-microvolt = <1450000>; > + regulator-ramp-delay = <20000>; > + regulator-name = "DA9063_CORE"; > + regulator-always-on; > + }; > + > + vddsoc_reg: bcore2 { > + regulator-min-microvolt = <1100000>; > + regulator-max-microvolt = <1450000>; > + regulator-ramp-delay = <20000>; > + regulator-name = "DA9063_SOC"; > + regulator-always-on; > + }; > + > + vdd_ddr3_reg: bpro { > + regulator-min-microvolt = <1500000>; > + regulator-max-microvolt = <1500000>; > + regulator-ramp-delay = <20000>; > + regulator-always-on; > + }; > + > + vdd_3v3_reg: bperi { > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-ramp-delay = <20000>; > + regulator-always-on; > + }; > + > + vdd_sata_reg: ldo3 { > + regulator-min-microvolt = <2500000>; > + regulator-max-microvolt = <2500000>; > + regulator-always-on; > + }; > + vdd_mipi_reg: ldo4 { > + regulator-min-microvolt = <2500000>; > + regulator-max-microvolt = <2500000>; > + regulator-always-on; > + }; > + > + vdd_mx6_snvs_reg: ldo5 { > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + regulator-always-on; > + }; > + > + vdd_hdmi_reg: ldo6 { > + regulator-min-microvolt = <2500000>; > + regulator-max-microvolt = <2500000>; > + regulator-always-on; > + regulator-boot-on; > + }; > + > + vdd_pcie_reg: ldo7 { > + regulator-min-microvolt = <2500000>; > + regulator-max-microvolt = <2500000>; > + regulator-always-on; > + }; > + > + vdd_1V8_reg: ldo8 { > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <1800000>; > + regulator-always-on; > + }; > + > + vdd_3V3_sdc_reg: ldo9 { > + regulator-min-microvolt = <1800000>; > + regulator-max-microvolt = <3300000>; > + regulator-always-on; > + }; > + > + vdd_1V2_reg: ldo10 { > + regulator-min-microvolt = <1200000>; > + regulator-max-microvolt = <1200000>; > + regulator-always-on; > + }; > + }; > + }; > +}; > + > +&uart1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart1>; > + status = "okay"; > +}; > + > +&uart2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart2>; > +}; > + > +&uart3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart3>; > +}; > + > +&uart4 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart4>; > +}; > + > +&uart5 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart5>; > +}; > + > +&fec { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_enet>; > + phy-mode = "rgmii"; > + phy-reset-gpios = <&gpio5 20 GPIO_ACTIVE_LOW>; > + phy-reset-duration = <50>; > + phy-supply = <&vdd_1V8_reg>; > + phy-handle = <&ksz9031>; > + status = "okay"; > + > + > + mdio { > + #address-cells = <1>; > + #size-cells = <0>; > + > + ksz9031: phy@0 { > + compatible = "ethernet-phy-ieee802.3-c22"; > + reg = <0>; > + interrupt-parent = <&gpio1>; > + interrupts = <30 IRQ_TYPE_EDGE_FALLING>; > + rxdv-skew-ps = <480>; > + txen-skew-ps = <480>; > + rxd0-skew-ps = <480>; > + rxd1-skew-ps = <480>; > + rxd2-skew-ps = <480>; > + rxd3-skew-ps = <480>; > + txd0-skew-ps = <420>; > + txd1-skew-ps = <420>; > + txd2-skew-ps = <360>; > + txd3-skew-ps = <360>; > + txc-skew-ps = <1020>; > + rxc-skew-ps = <960>; > + }; > + }; > +}; > + > + > +&usdhc3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usdhc3>; > + non-removable; > + bus-width = <8>; > + status = "okay"; > +}; > + > +&pcie { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pcie_ctrl>; > + reset-gpio = <&gpio7 12 GPIO_ACTIVE_LOW>; > + disable-gpio = <&gpio2 22 GPIO_ACTIVE_LOW>; > +}; > + > +&i2c2 { > + clock-frequency = <100000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c2>; > +}; > + > +&usdhc1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usdhc1>; > + fsl,wp-controller; > +}; > + > +&usdhc2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usdhc2>; > + fsl,wp-controller; > +}; > + > + > +&ipu1_di0_disp0 { > + remote-endpoint = <&rgb_encoder_in>; > +}; > + > +&pwm1 { > + status = "okay"; > +}; > + > +&pwm3 { > + status = "okay"; > +}; > + > +&pwm4 { > + status = "okay"; > +}; > + > +&ecspi2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_ecspi2>; > + cs-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>, > + <&gpio2 26 GPIO_ACTIVE_HIGH>; > +}; > + > +&ecspi4 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_nor_flash>; > +}; > + > +&can1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_can1>; > +}; > + > +&can2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_can2>; > +}; > + > +&usbh1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usb_host1>; > +}; > + > +&usbotg { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_usb_otg>; > + vbus-supply = <®_usb_otg>; > + dr_mode = "peripheral"; > +}; > + > +/******device power Management*********/ > + > +&cpu0 { > + voltage-tolerance = <2>; > +}; > + > +®_arm { > + vin-supply = <&vddcore_reg>; > +}; > + > +®_soc { > + vin-supply = <&vddsoc_reg>; > +}; > + > +®_pu { > + vin-supply = <&vddsoc_reg>; > +}; > + > + > + > +/*******Disabled HW following***********/ > + > + > +&weim { > + status = "disabled"; > +}; Isn't weim disabled by default? Shawn > + > +&snvs_rtc { > + status = "disabled"; > +}; > -- > 2.11.0 >