From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from mx2.suse.de ([195.135.220.15]) by Galois.linutronix.de with esmtps (TLS1.0:DHE_RSA_CAMELLIA_256_CBC_SHA1:256) (Exim 4.80) (envelope-from ) id 1fAifr-0000A8-TR for speck@linutronix.de; Mon, 23 Apr 2018 23:07:00 +0200 Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 2C77DAB4B for ; Mon, 23 Apr 2018 21:06:54 +0000 (UTC) Date: Mon, 23 Apr 2018 23:06:43 +0200 From: Borislav Petkov Subject: [MODERATED] Re: [PATCH v3 06/10] [PATCH v3 6/9] Linux Patch #6 Message-ID: <20180423210643.GO24245@pd.tnic> References: <20180423171426.795385641@dhcp-10-159-147-220.vpn.oracle.com> <20180423183459.GL24245@pd.tnic> MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: speck@linutronix.de List-ID: On Mon, Apr 23, 2018 at 10:45:10PM +0200, speck for Jiri Kosina wrote: > Don't we really want it to appear in /proc/cpuinfo though? >=20 > At the end of the day, it really is about toggling an internal CPU feature = > behavior, so I'd say it belongs there. >=20 > We even have PTI there, and this is way more actually really internal to=20 > the CPU. Well, the thing is that other CPUs have store bypassing too but they don't necessarily have the disabling bit. So if anything, we should use the X86_BUG_CPU_SPEC_STORE_BYPASS bit so that it appears in the bugs: line. I mean, one of the two: X86_FEATURE_STBUF_BYPASS or X86_BUG_CPU_SPEC_STORE_BYPASS is redundant AFAICT so we can stick with the X86_BUG one. Also, we have the state in /sys/devices/system/cpu/vulnerabilities/ too, in case something needs it. --=20 Regards/Gruss, Boris. SUSE Linux GmbH, GF: Felix Imend=C3=B6rffer, Jane Smithard, Graham Norton, HR= B 21284 (AG N=C3=BCrnberg) --=20