From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from aserp2130.oracle.com ([141.146.126.79]) by Galois.linutronix.de with esmtps (TLS1.2:RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1fBONR-0005jj-7t for speck@linutronix.de; Wed, 25 Apr 2018 19:38:46 +0200 Received: from pps.filterd (aserp2130.oracle.com [127.0.0.1]) by aserp2130.oracle.com (8.16.0.22/8.16.0.22) with SMTP id w3PHKtij103483 for ; Wed, 25 Apr 2018 17:38:38 GMT Received: from aserv0021.oracle.com (aserv0021.oracle.com [141.146.126.233]) by aserp2130.oracle.com with ESMTP id 2hftty80ey-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Wed, 25 Apr 2018 17:38:38 +0000 Received: from aserv0121.oracle.com (aserv0121.oracle.com [141.146.126.235]) by aserv0021.oracle.com (8.14.4/8.14.4) with ESMTP id w3PHccZs005198 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Wed, 25 Apr 2018 17:38:38 GMT Received: from abhmp0015.oracle.com (abhmp0015.oracle.com [141.146.116.21]) by aserv0121.oracle.com (8.14.4/8.13.8) with ESMTP id w3PHccLH028935 for ; Wed, 25 Apr 2018 17:38:38 GMT Date: Wed, 25 Apr 2018 13:38:32 -0400 From: Konrad Rzeszutek Wilk Subject: [MODERATED] Re: [PATCH v4 06/10] [PATCH v4 6/9] Linux Patch #6 Message-ID: <20180425173141.GA1847@localhost.localdomain> References: <20180424031751.311879235@dhcp-10-159-147-220.vpn.oracle.com> MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Wed, Apr 25, 2018 at 09:51:52AM -0700, speck for Tim Chen wrote: > > Future Intel CPUs that do not have speculative store bypass vulnerability will > turn on bit 4 in MSR 0x10a (MSR_IA32_ARCH_CAPABILITIES). Is it going to be called 'RDS' or SSB'? I am going to assume ARCH_CAP_RDS_NO > > So we should add this check. > > Suggested code changes below. Let me roll it in (removed the {} in the cpu_set_bug_bits). > > Tim > > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h > index 96ae1e7..c28af75 100644 > --- a/arch/x86/include/asm/msr-index.h > +++ b/arch/x86/include/asm/msr-index.h > @@ -69,6 +69,7 @@ > #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a > #define ARCH_CAP_RDCL_NO (1 << 0) /* Not susceptible to Meltdown */ > #define ARCH_CAP_IBRS_ALL (1 << 1) /* Enhanced IBRS support */ > +#define ARCH_CAP_SSB_NO (1 << 4) /* Not susceptible to speculative store bypass */ > > #define MSR_IA32_BBL_CR_CTL 0x00000119 > #define MSR_IA32_BBL_CR_CTL3 0x0000011e > diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c > index 581eb04..de7fb75 100644 > --- a/arch/x86/kernel/cpu/common.c > +++ b/arch/x86/kernel/cpu/common.c > @@ -944,8 +944,13 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) > { > u64 ia32_cap = 0; > > - if (!x86_match_cpu(cpu_no_spec_store_bypass)) > + if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES)) > + rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); > + > + if (!x86_match_cpu(cpu_no_spec_store_bypass) && > + !(ia32_cap & ARCH_CAP_SSB_NO)) { > setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS); > + } > > if (x86_match_cpu(cpu_no_speculation)) > return; > @@ -956,9 +961,6 @@ static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c) > if (x86_match_cpu(cpu_no_meltdown)) > return; > > - if (cpu_has(c, X86_FEATURE_ARCH_CAPABILITIES)) > - rdmsrl(MSR_IA32_ARCH_CAPABILITIES, ia32_cap); > - > /* Rogue Data Cache Load? No! */ > if (ia32_cap & ARCH_CAP_RDCL_NO) > return; > -- > 2.7.4 >