From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from mx2.suse.de ([195.135.220.15]) by Galois.linutronix.de with esmtps (TLS1.0:DHE_RSA_CAMELLIA_256_CBC_SHA1:256) (Exim 4.80) (envelope-from ) id 1fBdtO-0002Bk-3N for speck@linutronix.de; Thu, 26 Apr 2018 12:12:46 +0200 Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id CA2F7ADF9 for ; Thu, 26 Apr 2018 10:12:40 +0000 (UTC) Date: Thu, 26 Apr 2018 12:12:28 +0200 From: Borislav Petkov Subject: [MODERATED] Re: [PATCH v5 05/11] [PATCH v5 05/10] Linux Patch #5 Message-ID: <20180426101228.GC15043@pd.tnic> References: <20180426020546.059234583@localhost.localdomain> MIME-Version: 1.0 In-Reply-To: <20180426020546.059234583@localhost.localdomain> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: speck@linutronix.de List-ID: On Wed, Apr 25, 2018 at 10:04:20PM -0400, speck for konrad.wilk_at_oracle.com= wrote: > x86/bugs: Expose the /sys/../spec_store_bypass and X86_BUG_SPEC_STORE_BYPASS >=20 > It does not do much except show the words 'Vulnerable' for recent x86 > cores. Intel cores prior to Nehalem are known not to be vulnerable, and > so are some Atoms and some Xeon Phi. >=20 > It assumes that older Cyrix, Centaur, etc. cores are immune. >=20 > Signed-off-by: Konrad Rzeszutek Wilk > --- > v1.3: Remove AMD > s/md/mdd/ > v1.4: s/mdd/sbb/ > v3: s/SSB/SPEC_STORE_BYPASS > Rework the logic in cpu_set_bug_bits to be inverse. > v4: Expanded the not affected array > - s/X86_BUG_CPU_SPEC_STORE_BYPASS/X86_BUG_SPEC_STORE_BYPASS/ > --- > arch/x86/include/asm/cpufeatures.h | 1 + > arch/x86/kernel/cpu/bugs.c | 5 +++++ > arch/x86/kernel/cpu/common.c | 20 ++++++++++++++++++++ > drivers/base/cpu.c | 8 ++++++++ > include/linux/cpu.h | 2 ++ > 5 files changed, 36 insertions(+) Reviewed-by: Borislav Petkov --=20 Regards/Gruss, Boris. SUSE Linux GmbH, GF: Felix Imend=C3=B6rffer, Jane Smithard, Graham Norton, HR= B 21284 (AG N=C3=BCrnberg) --=20