From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from mga03.intel.com ([134.134.136.65]) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1fBqsq-00066H-Vo for speck@linutronix.de; Fri, 27 Apr 2018 02:05:06 +0200 Date: Thu, 26 Apr 2018 17:05:01 -0700 From: Andi Kleen Subject: [MODERATED] Re: [PATCH 1/6] Patch 1 Message-ID: <20180427000501.GB75137@tassilo.jf.intel.com> References: <20180425181152.GK14273@tassilo.jf.intel.com> <20180425185140.GL14273@tassilo.jf.intel.com> <20180425211901.GN14273@tassilo.jf.intel.com> <20180425231238.GO14273@tassilo.jf.intel.com> <20180426135429.GT17484@dhcp22.suse.cz> MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: > That, in turn, means that if you have a desktop chip with only 40 bits of > physical addressing, now that the offset starts at bit 9, you still have > to have 30 bits of offset actually *in use* until bit 39 ends up being > clear. Here are the cases for modern Intel CPUs: Nehalem Client 39 >=0.25TB Nehalem Server 44 >=8TB SandyBridge/IvyBridge/Haswell/Broadwell/Skylake 46 >=32TB In general anything newer has 46 bits > Anybody willing to test and/or double-check my math/logic? I did some tests and it works and seems to do the right thing. I'll use this patch in the next version of the patchkit. Thanks. -Andi