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Date: Sun, 29 Apr 2018 20:16:37 -0400
From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Subject: [MODERATED] Re: [patch V7 10/15] SBB 10
Message-ID: <20180430001631.GA27017@localhost.localdomain>
References: <20180429193045.711908246@linutronix.de>
 <20180429193938.293499564@linutronix.de>
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To: speck@linutronix.de
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..snip..
> @@ -52,7 +59,8 @@ void __init check_bugs(void)
>  
>  	/*
>  	 * Read the SPEC_CTRL MSR to account for reserved bits which may
> -	 * have unknown values.
> +	 * have unknown values. AMD64_LS_CFG msr is cached in the early AMD
> +	 * init code as it is not enumerated and depends on the family.
>  	 */
>  	if (boot_cpu_has(X86_FEATURE_IBRS))
>  		rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
> @@ -154,6 +162,14 @@ void x86_restore_host_spec_ctrl(u64 gues
>  }
>  EXPORT_SYMBOL_GPL(x86_restore_host_spec_ctrl);
>  
> +static void x86_amd_rds_enable(void)
> +{
> +	u64 msrval = x86_amd_ls_cfg_base | x86_amd_ls_cfg_rds_bit);
                                                                 ^- that
')' shouldn't be there.