From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v3,2/2] x86/mce: add CMCI support for Centaur CPUs From: Borislav Petkov Message-Id: <20180430094802.GF6509@pd.tnic> Date: Mon, 30 Apr 2018 11:48:02 +0200 To: David Wang Cc: tony.luck@intel.com, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, gregkh@linuxfoundation.org, x86@kernel.org, linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org, brucechang@via-alliance.com, cooperyan@zhaoxin.com, qiyuanwang@zhaoxin.com, benjaminpan@viatech.com, lukelin@viacpu.com, timguo@zhaoxin.com List-ID: T24gV2VkLCBBcHIgMjUsIDIwMTggYXQgMDY6MzM6NDBQTSArMDgwMCwgRGF2aWQgV2FuZyB3cm90 ZToKPiBOZXdlciBDZW50YXVyIHN1cHBvcnQgQ01DSSBtZWNobmlzbSwgd2hpY2ggaXMgY29tcGF0 aWJsZSB3aXRoIElOVEVMIENNQ0kuCj4gCj4gU2lnbmVkLW9mZi1ieTogRGF2aWQgV2FuZyA8ZGF2 aWR3YW5nQHpoYW94aW4uY29tPgo+IC0tLQo+ICBhcmNoL3g4Ni9rZXJuZWwvY3B1L21jaGVjay9t Y2UuYyB8IDIgKysKPiAgMSBmaWxlIGNoYW5nZWQsIDIgaW5zZXJ0aW9ucygrKQo+IAo+IGRpZmYg LS1naXQgYS9hcmNoL3g4Ni9rZXJuZWwvY3B1L21jaGVjay9tY2UuYyBiL2FyY2gveDg2L2tlcm5l bC9jcHUvbWNoZWNrL21jZS5jCj4gaW5kZXggMzhjY2FiOC4uZjlhNzI5NSAxMDA2NDQKPiAtLS0g YS9hcmNoL3g4Ni9rZXJuZWwvY3B1L21jaGVjay9tY2UuYwo+ICsrKyBiL2FyY2gveDg2L2tlcm5l bC9jcHUvbWNoZWNrL21jZS5jCj4gQEAgLTE3NTcsNiArMTc1Nyw4IEBAIHN0YXRpYyB2b2lkIF9f bWNoZWNrX2NwdV9pbml0X3ZlbmRvcihzdHJ1Y3QgY3B1aW5mb194ODYgKmMpCj4gIAkJfQo+ICAJ Y2FzZSBYODZfVkVORE9SX0NFTlRBVVI6Cj4gIAkJbWNlX2NlbnRhdXJfZmVhdHVyZV9pbml0KGMp Owo+ICsJCW1jZV9pbnRlbF9mZWF0dXJlX2luaXQoYyk7Cj4gKwkJbWNlX2FkanVzdF90aW1lciA9 IGNtY2lfaW50ZWxfYWRqdXN0X3RpbWVyOwoKVGhpcyB3b24ndCB3b3JrIGluIGNvbmZpZ3Mgd2l0 aCBDT05GSUdfWDg2X01DRV9JTlRFTCBkaXNhYmxlZC4KCllvdSBuZWVkIHRvIGRlZmluZSBDT05G SUdfWDg2X01DRV9DRU5UQVVSIG9yIHNvIHdoaWNoIGRlcGVuZHMgb24KQ09ORklHX0NQVV9TVVBf Q0VOVEFVUiBhbmQgQ09ORklHX1g4Nl9NQ0VfSU5URUwgYW5kIHdoaWNoIHRoZW4gbWFrZXMKc3Vy ZSB0aGUgaW50ZWwgQ01DSSBldCBhbCBzdHVmZiBpcyBlbmFibGVkLgo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Google-Smtp-Source: AB8JxZp9Ozhs9rQBStt4QT65NnmZ2dQdgSj8Cr6i0jD+pPPtiuSzrALHiYH63NImUOYN+EyzQuCS ARC-Seal: i=1; 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mx.google.com; spf=pass (google.com: domain of bp@alien8.de designates 2a01:4f8:190:11c2::b:1457 as permitted sender) smtp.mailfrom=bp@alien8.de Authentication-Results: mx.google.com; spf=pass (google.com: domain of bp@alien8.de designates 2a01:4f8:190:11c2::b:1457 as permitted sender) smtp.mailfrom=bp@alien8.de Date: Mon, 30 Apr 2018 11:48:02 +0200 From: Borislav Petkov To: David Wang Cc: tony.luck@intel.com, tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, gregkh@linuxfoundation.org, x86@kernel.org, linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org, brucechang@via-alliance.com, cooperyan@zhaoxin.com, qiyuanwang@zhaoxin.com, benjaminpan@viatech.com, lukelin@viacpu.com, timguo@zhaoxin.com Subject: Re: [PATCH v3 2/2] x86/mce: add CMCI support for Centaur CPUs Message-ID: <20180430094802.GF6509@pd.tnic> References: <1524652420-17330-1-git-send-email-davidwang@zhaoxin.com> <1524652420-17330-3-git-send-email-davidwang@zhaoxin.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <1524652420-17330-3-git-send-email-davidwang@zhaoxin.com> User-Agent: Mutt/1.9.3 (2018-01-21) X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1598713954946471832?= X-GMAIL-MSGID: =?utf-8?q?1599164085498266980?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: On Wed, Apr 25, 2018 at 06:33:40PM +0800, David Wang wrote: > Newer Centaur support CMCI mechnism, which is compatible with INTEL CMCI. > > Signed-off-by: David Wang > --- > arch/x86/kernel/cpu/mcheck/mce.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c > index 38ccab8..f9a7295 100644 > --- a/arch/x86/kernel/cpu/mcheck/mce.c > +++ b/arch/x86/kernel/cpu/mcheck/mce.c > @@ -1757,6 +1757,8 @@ static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) > } > case X86_VENDOR_CENTAUR: > mce_centaur_feature_init(c); > + mce_intel_feature_init(c); > + mce_adjust_timer = cmci_intel_adjust_timer; This won't work in configs with CONFIG_X86_MCE_INTEL disabled. You need to define CONFIG_X86_MCE_CENTAUR or so which depends on CONFIG_CPU_SUP_CENTAUR and CONFIG_X86_MCE_INTEL and which then makes sure the intel CMCI et al stuff is enabled. -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply.