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From: Eduardo Habkost <ehabkost@redhat.com>
To: Jingqi Liu <jingqi.liu@intel.com>
Cc: qemu-devel@nongnu.org, pbonzini@redhat.com, rth@twiddle.net
Subject: Re: [Qemu-devel] [PATCH] x86/cpu: Enable CLDEMOTE(Demote Cache Line) cpu feature
Date: Thu, 3 May 2018 00:04:57 -0300	[thread overview]
Message-ID: <20180503030457.GB25013@localhost.localdomain> (raw)
In-Reply-To: <1525406253-54846-1-git-send-email-jingqi.liu@intel.com>

On Fri, May 04, 2018 at 11:57:33AM +0800, Jingqi Liu wrote:
> The CLDEMOTE instruction hints to hardware that the cache line that
> contains the linear address should be moved("demoted") from
> the cache(s) closest to the processor core to a level more distant
> from the processor core. This may accelerate subsequent accesses
> to the line by other cores in the same coherence domain,
> especially if the line was written by the core that demotes the line.
> 
> Intel Snow Ridge has added new cpu feature, CLDEMOTE.
> The new cpu feature needs to be exposed to guest VM.
> 
> The bit definition:
> CPUID.(EAX=7,ECX=0):ECX[bit 25] CLDEMOTE
> 
> The release document ref below link:
> https://software.intel.com/sites/default/files/managed/c5/15/\
> architecture-instruction-set-extensions-programming-reference.pdf
> 
> Signed-off-by: Jingqi Liu <jingqi.liu@intel.com>

Thanks.  Do you have a pointer to the corresponding
GET_SUPPORTED_CPUID patch in KVM?

-- 
Eduardo

  reply	other threads:[~2018-05-03  3:05 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-04  3:57 [Qemu-devel] [PATCH] x86/cpu: Enable CLDEMOTE(Demote Cache Line) cpu feature Jingqi Liu
2018-05-03  3:04 ` Eduardo Habkost [this message]
2018-05-03  5:42   ` Liu, Jingqi
2018-05-07 18:45 ` Eduardo Habkost

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