From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from mx2.suse.de ([195.135.220.15]) by Galois.linutronix.de with esmtps (TLS1.0:DHE_RSA_CAMELLIA_256_CBC_SHA1:256) (Exim 4.80) (envelope-from ) id 1fIAJh-0000lW-Ui for speck@linutronix.de; Mon, 14 May 2018 12:02:54 +0200 Received: from relay1.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 7782EAEB3 for ; Mon, 14 May 2018 10:02:42 +0000 (UTC) Date: Mon, 14 May 2018 12:02:32 +0200 From: Borislav Petkov Subject: [MODERATED] Re: [patch 03/15] Hidden 3 Message-ID: <20180514100232.GC18407@pd.tnic> References: <20180513140048.543641807@linutronix.de> <20180513140538.470697861@linutronix.de> MIME-Version: 1.0 In-Reply-To: <20180513140538.470697861@linutronix.de> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: speck@linutronix.de List-ID: On Sun, May 13, 2018 at 04:00:51PM +0200, speck for Thomas Gleixner wrote: > Subject: [patch 03/15] x86/cpufeatures: Disentangle MSR_SPEC_CTRL enumerati= on from IBRS > From: Thomas Gleixner >=20 > The availability of the SPEC_CTRL MSR is enumerated by a CPUID bit on > Intel and implied by IBRS or STIBP support on AMD. That's just confusing > and in case an AMD CPU has IBRS not supported because the underlying > problem has been fixed but has another bit valid in the SPEC_CTRL MSR, > the thing falls apart. >=20 > Add a synthetic feature bit X86_FEATURE_MSR_SPEC_CTRL to denote the > availability on both Intel and AMD. >=20 > Signed-off-by: Thomas Gleixner > --- > arch/x86/include/asm/cpufeatures.h | 1 + > arch/x86/kernel/cpu/bugs.c | 18 +++++++++++------- > arch/x86/kernel/cpu/common.c | 9 +++++++-- > arch/x86/kernel/cpu/intel.c | 1 + > 4 files changed, 20 insertions(+), 9 deletions(-) Reviewed-by: Borislav Petkov --=20 Regards/Gruss, Boris. SUSE Linux GmbH, GF: Felix Imend=C3=B6rffer, Jane Smithard, Graham Norton, HR= B 21284 (AG N=C3=BCrnberg) --=20