From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from mx2.suse.de ([195.135.220.15]) by Galois.linutronix.de with esmtps (TLS1.0:DHE_RSA_CAMELLIA_256_CBC_SHA1:256) (Exim 4.80) (envelope-from ) id 1fIBOO-0001vB-L6 for speck@linutronix.de; Mon, 14 May 2018 13:11:50 +0200 Received: from relay2.suse.de (charybdis-ext.suse.de [195.135.220.254]) by mx2.suse.de (Postfix) with ESMTP id 01679AD97 for ; Mon, 14 May 2018 11:11:42 +0000 (UTC) Date: Mon, 14 May 2018 13:11:28 +0200 From: Borislav Petkov Subject: [MODERATED] Re: [patch 04/15] Hidden 4 Message-ID: <20180514111128.GG18407@pd.tnic> References: <20180513140048.543641807@linutronix.de> <20180513140538.551893231@linutronix.de> MIME-Version: 1.0 In-Reply-To: <20180513140538.551893231@linutronix.de> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable To: speck@linutronix.de List-ID: On Sun, May 13, 2018 at 04:00:52PM +0200, speck for Thomas Gleixner wrote: > Subject: [patch 04/15] x86/cpufeatures: Disentangle SSBD enumeration > From: Thomas Gleixner >=20 > The SSBD enumeration is similarly to the other bits magically shared > between Intel and AMD though the mechanisms are different. >=20 > Make X86_FEATURE_SSBD synthetic and set it depending on the vendor specific > features or family dependent setup. >=20 > Change the Intel bit to X86_FEATURE_SPEC_CTRL_SSBD to denote that SSBD is > controlled via MSR_SPEC_CTRL and fix up the usage sites. >=20 > Signed-off-by: Thomas Gleixner > --- > arch/x86/include/asm/cpufeatures.h | 7 +++---- > arch/x86/kernel/cpu/amd.c | 7 +------ > arch/x86/kernel/cpu/bugs.c | 10 +++++----- > arch/x86/kernel/cpu/common.c | 3 +++ > arch/x86/kernel/process.c | 2 +- > 5 files changed, 13 insertions(+), 16 deletions(-) Reviewed-by: Borislav Petkov --=20 Regards/Gruss, Boris. SUSE Linux GmbH, GF: Felix Imend=C3=B6rffer, Jane Smithard, Graham Norton, HR= B 21284 (AG N=C3=BCrnberg) --=20