diff for duplicates of <20180515074042.GP26863@dragon> diff --git a/a/1.txt b/N1/1.txt index cf60b42..f97202a 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -4,9 +4,9 @@ On Mon, May 14, 2018 at 10:31:54AM -0300, Fabio Estevam wrote: > Remove unit-address and reg property from anatop regulators to fix > the following DTC warnings with W=1: > -> arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (unique_unit_address): /soc/aips-bus at 2000000/anatop at 20c8000/regulator-vddcore at 20c8140: duplicate unit-address (also used in node /soc/aips-bus at 2000000/anatop at 20c8000/regulator-vddpu at 20c8140) -> arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (unique_unit_address): /soc/aips-bus at 2000000/anatop at 20c8000/regulator-vddcore at 20c8140: duplicate unit-address (also used in node /soc/aips-bus at 2000000/anatop at 20c8000/regulator-vddsoc at 20c8140) -> arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (unique_unit_address): /soc/aips-bus at 2000000/anatop at 20c8000/regulator-vddpu at 20c8140: duplicate unit-address (also used in node /soc/aips-bus at 2000000/anatop at 20c8000/regulator-vddsoc at 20c8140) +> arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (unique_unit_address): /soc/aips-bus@2000000/anatop@20c8000/regulator-vddcore@20c8140: duplicate unit-address (also used in node /soc/aips-bus@2000000/anatop@20c8000/regulator-vddpu@20c8140) +> arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (unique_unit_address): /soc/aips-bus@2000000/anatop@20c8000/regulator-vddcore@20c8140: duplicate unit-address (also used in node /soc/aips-bus@2000000/anatop@20c8000/regulator-vddsoc@20c8140) +> arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (unique_unit_address): /soc/aips-bus@2000000/anatop@20c8000/regulator-vddpu@20c8140: duplicate unit-address (also used in node /soc/aips-bus@2000000/anatop@20c8000/regulator-vddsoc@20c8140) > > Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> > --- @@ -39,7 +39,7 @@ Shawn > - #address-cells = <1>; > - #size-cells = <0>; > -> - regulator-1p1 at 20c8110 { +> - regulator-1p1@20c8110 { > - reg = <0x20c8110>; > + regulator-1p1 { > compatible = "fsl,anatop-regulator"; @@ -49,7 +49,7 @@ Shawn > anatop-enable-bit = <0>; > }; > -> - regulator-3p0 at 20c8120 { +> - regulator-3p0@20c8120 { > - reg = <0x20c8120>; > + regulator-3p0 { > compatible = "fsl,anatop-regulator"; @@ -59,7 +59,7 @@ Shawn > anatop-enable-bit = <0>; > }; > -> - regulator-2p5 at 20c8130 { +> - regulator-2p5@20c8130 { > - reg = <0x20c8130>; > + regulator-2p5 { > compatible = "fsl,anatop-regulator"; @@ -69,7 +69,7 @@ Shawn > anatop-enable-bit = <0>; > }; > -> - reg_arm: regulator-vddcore at 20c8140 { +> - reg_arm: regulator-vddcore@20c8140 { > - reg = <0x20c8140>; > + reg_arm: regulator-vddcore { > compatible = "fsl,anatop-regulator"; @@ -79,7 +79,7 @@ Shawn > anatop-max-voltage = <1450000>; > }; > -> - reg_pu: regulator-vddpu at 20c8140 { +> - reg_pu: regulator-vddpu@20c8140 { > - reg = <0x20c8140>; > + reg_pu: regulator-vddpu { > compatible = "fsl,anatop-regulator"; @@ -89,7 +89,7 @@ Shawn > anatop-max-voltage = <1450000>; > }; > -> - reg_soc: regulator-vddsoc at 20c8140 { +> - reg_soc: regulator-vddsoc@20c8140 { > - reg = <0x20c8140>; > + reg_soc: regulator-vddsoc { > compatible = "fsl,anatop-regulator"; @@ -106,7 +106,7 @@ Shawn > - #address-cells = <1>; > - #size-cells = <0>; > -> - regulator-1p1 at 20c8110 { +> - regulator-1p1@20c8110 { > - reg = <0x20c8110>; > + regulator-1p1 { > compatible = "fsl,anatop-regulator"; @@ -116,7 +116,7 @@ Shawn > anatop-enable-bit = <0>; > }; > -> - regulator-3p0 at 20c8120 { +> - regulator-3p0@20c8120 { > - reg = <0x20c8120>; > + regulator-3p0 { > compatible = "fsl,anatop-regulator"; @@ -126,7 +126,7 @@ Shawn > anatop-enable-bit = <0>; > }; > -> - regulator-2p5 at 20c8130 { +> - regulator-2p5@20c8130 { > - reg = <0x20c8130>; > + regulator-2p5 { > compatible = "fsl,anatop-regulator"; @@ -136,7 +136,7 @@ Shawn > anatop-enable-bit = <0>; > }; > -> - reg_arm: regulator-vddcore at 20c8140 { +> - reg_arm: regulator-vddcore@20c8140 { > - reg = <0x20c8140>; > + reg_arm: regulator-vddcore { > compatible = "fsl,anatop-regulator"; @@ -146,7 +146,7 @@ Shawn > anatop-max-voltage = <1450000>; > }; > -> - reg_pu: regulator-vddpu at 20c8140 { +> - reg_pu: regulator-vddpu@20c8140 { > - reg = <0x20c8140>; > + reg_pu: regulator-vddpu { > compatible = "fsl,anatop-regulator"; @@ -156,7 +156,7 @@ Shawn > anatop-max-voltage = <1450000>; > }; > -> - reg_soc: regulator-vddsoc at 20c8140 { +> - reg_soc: regulator-vddsoc@20c8140 { > - reg = <0x20c8140>; > + reg_soc: regulator-vddsoc { > compatible = "fsl,anatop-regulator"; @@ -173,7 +173,7 @@ Shawn > - #address-cells = <1>; > - #size-cells = <0>; > -> - regulator-1p1 at 20c8110 { +> - regulator-1p1@20c8110 { > - reg = <0x20c8110>; > + regulator-1p1 { > compatible = "fsl,anatop-regulator"; @@ -183,7 +183,7 @@ Shawn > anatop-enable-bit = <0>; > }; > -> - regulator-3p0 at 20c8120 { +> - regulator-3p0@20c8120 { > - reg = <0x20c8120>; > + regulator-3p0 { > compatible = "fsl,anatop-regulator"; @@ -193,7 +193,7 @@ Shawn > anatop-enable-bit = <0>; > }; > -> - regulator-2p5 at 20c8130 { +> - regulator-2p5@20c8130 { > - reg = <0x20c8130>; > + regulator-2p5 { > compatible = "fsl,anatop-regulator"; @@ -203,7 +203,7 @@ Shawn > anatop-enable-bit = <0>; > }; > -> - reg_arm: regulator-vddcore at 20c8140 { +> - reg_arm: regulator-vddcore@20c8140 { > - reg = <0x20c8140>; > + reg_arm: regulator-vddcore { > compatible = "fsl,anatop-regulator"; @@ -213,7 +213,7 @@ Shawn > anatop-max-voltage = <1450000>; > }; > -> - reg_pcie: regulator-vddpcie at 20c8140 { +> - reg_pcie: regulator-vddpcie@20c8140 { > - reg = <0x20c8140>; > + reg_pcie: regulator-vddpcie { > compatible = "fsl,anatop-regulator"; @@ -223,7 +223,7 @@ Shawn > anatop-max-voltage = <1450000>; > }; > -> - reg_soc: regulator-vddsoc at 20c8140 { +> - reg_soc: regulator-vddsoc@20c8140 { > - reg = <0x20c8140>; > + reg_soc: regulator-vddsoc { > compatible = "fsl,anatop-regulator"; @@ -240,7 +240,7 @@ Shawn > - #address-cells = <1>; > - #size-cells = <0>; > -> - reg_3p0: regulator-3p0 at 20c8110 { +> - reg_3p0: regulator-3p0@20c8110 { > - reg = <0x20c8110>; > + reg_3p0: regulator-3p0 { > compatible = "fsl,anatop-regulator"; @@ -250,7 +250,7 @@ Shawn > anatop-enable-bit = <0>; > }; > -> - reg_arm: regulator-vddcore at 20c8140 { +> - reg_arm: regulator-vddcore@20c8140 { > - reg = <0x20c8140>; > + reg_arm: regulator-vddcore { > compatible = "fsl,anatop-regulator"; @@ -260,7 +260,7 @@ Shawn > anatop-max-voltage = <1450000>; > }; > -> - reg_soc: regulator-vddsoc at 20c8140 { +> - reg_soc: regulator-vddsoc@20c8140 { > - reg = <0x20c8140>; > + reg_soc: regulator-vddsoc { > compatible = "fsl,anatop-regulator"; @@ -277,7 +277,7 @@ Shawn > - #address-cells = <1>; > - #size-cells = <0>; > -> - reg_1p0d: regulator-vdd1p0d at 30360210 { +> - reg_1p0d: regulator-vdd1p0d@30360210 { > - reg = <0x30360210>; > + reg_1p0d: regulator-vdd1p0d { > compatible = "fsl,anatop-regulator"; @@ -287,7 +287,7 @@ Shawn > anatop-enable-bit = <0>; > }; > -> - reg_1p2: regulator-vdd1p2 at 30360220 { +> - reg_1p2: regulator-vdd1p2@30360220 { > - reg = <0x30360220>; > + reg_1p2: regulator-vdd1p2 { > compatible = "fsl,anatop-regulator"; diff --git a/a/content_digest b/N1/content_digest index 72b59b9..a16b31a 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,8 +1,12 @@ "ref\01526304714-23821-1-git-send-email-festevam@gmail.com\0" - "From\0shawnguo@kernel.org (Shawn Guo)\0" - "Subject\0[PATCH v2] ARM: dts: imx6/7: Remove unit-address from anatop regulators\0" + "From\0Shawn Guo <shawnguo@kernel.org>\0" + "Subject\0Re: [PATCH v2] ARM: dts: imx6/7: Remove unit-address from anatop regulators\0" "Date\0Tue, 15 May 2018 15:40:44 +0800\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Fabio Estevam <festevam@gmail.com>\0" + "Cc\0Fabio Estevam <fabio.estevam@nxp.com>" + devicetree@vger.kernel.org + robh+dt@kernel.org + " linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On Mon, May 14, 2018 at 10:31:54AM -0300, Fabio Estevam wrote:\n" @@ -11,9 +15,9 @@ "> Remove unit-address and reg property from anatop regulators to fix\n" "> the following DTC warnings with W=1:\n" "> \n" - "> arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (unique_unit_address): /soc/aips-bus at 2000000/anatop at 20c8000/regulator-vddcore at 20c8140: duplicate unit-address (also used in node /soc/aips-bus at 2000000/anatop at 20c8000/regulator-vddpu at 20c8140)\n" - "> arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (unique_unit_address): /soc/aips-bus at 2000000/anatop at 20c8000/regulator-vddcore at 20c8140: duplicate unit-address (also used in node /soc/aips-bus at 2000000/anatop at 20c8000/regulator-vddsoc at 20c8140)\n" - "> arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (unique_unit_address): /soc/aips-bus at 2000000/anatop at 20c8000/regulator-vddpu at 20c8140: duplicate unit-address (also used in node /soc/aips-bus at 2000000/anatop at 20c8000/regulator-vddsoc at 20c8140)\n" + "> arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (unique_unit_address): /soc/aips-bus@2000000/anatop@20c8000/regulator-vddcore@20c8140: duplicate unit-address (also used in node /soc/aips-bus@2000000/anatop@20c8000/regulator-vddpu@20c8140)\n" + "> arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (unique_unit_address): /soc/aips-bus@2000000/anatop@20c8000/regulator-vddcore@20c8140: duplicate unit-address (also used in node /soc/aips-bus@2000000/anatop@20c8000/regulator-vddsoc@20c8140)\n" + "> arch/arm/boot/dts/imx6dl-apf6dev.dtb: Warning (unique_unit_address): /soc/aips-bus@2000000/anatop@20c8000/regulator-vddpu@20c8140: duplicate unit-address (also used in node /soc/aips-bus@2000000/anatop@20c8000/regulator-vddsoc@20c8140)\n" "> \n" "> Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>\n" "> ---\n" @@ -46,7 +50,7 @@ "> -\t\t\t\t#address-cells = <1>;\n" "> -\t\t\t\t#size-cells = <0>;\n" "> \n" - "> -\t\t\t\tregulator-1p1 at 20c8110 {\n" + "> -\t\t\t\tregulator-1p1@20c8110 {\n" "> -\t\t\t\t\treg = <0x20c8110>;\n" "> +\t\t\t\tregulator-1p1 {\n" "> \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -56,7 +60,7 @@ "> \t\t\t\t\tanatop-enable-bit = <0>;\n" "> \t\t\t\t};\n" "> \n" - "> -\t\t\t\tregulator-3p0 at 20c8120 {\n" + "> -\t\t\t\tregulator-3p0@20c8120 {\n" "> -\t\t\t\t\treg = <0x20c8120>;\n" "> +\t\t\t\tregulator-3p0 {\n" "> \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -66,7 +70,7 @@ "> \t\t\t\t\tanatop-enable-bit = <0>;\n" "> \t\t\t\t};\n" "> \n" - "> -\t\t\t\tregulator-2p5 at 20c8130 {\n" + "> -\t\t\t\tregulator-2p5@20c8130 {\n" "> -\t\t\t\t\treg = <0x20c8130>;\n" "> +\t\t\t\tregulator-2p5 {\n" "> \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -76,7 +80,7 @@ "> \t\t\t\t\tanatop-enable-bit = <0>;\n" "> \t\t\t\t};\n" "> \n" - "> -\t\t\t\treg_arm: regulator-vddcore at 20c8140 {\n" + "> -\t\t\t\treg_arm: regulator-vddcore@20c8140 {\n" "> -\t\t\t\t\treg = <0x20c8140>;\n" "> +\t\t\t\treg_arm: regulator-vddcore {\n" "> \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -86,7 +90,7 @@ "> \t\t\t\t\tanatop-max-voltage = <1450000>;\n" "> \t\t\t\t};\n" "> \n" - "> -\t\t\t\treg_pu: regulator-vddpu at 20c8140 {\n" + "> -\t\t\t\treg_pu: regulator-vddpu@20c8140 {\n" "> -\t\t\t\t\treg = <0x20c8140>;\n" "> +\t\t\t\treg_pu: regulator-vddpu {\n" "> \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -96,7 +100,7 @@ "> \t\t\t\t\tanatop-max-voltage = <1450000>;\n" "> \t\t\t\t};\n" "> \n" - "> -\t\t\t\treg_soc: regulator-vddsoc at 20c8140 {\n" + "> -\t\t\t\treg_soc: regulator-vddsoc@20c8140 {\n" "> -\t\t\t\t\treg = <0x20c8140>;\n" "> +\t\t\t\treg_soc: regulator-vddsoc {\n" "> \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -113,7 +117,7 @@ "> -\t\t\t\t#address-cells = <1>;\n" "> -\t\t\t\t#size-cells = <0>;\n" "> \n" - "> -\t\t\t\tregulator-1p1 at 20c8110 {\n" + "> -\t\t\t\tregulator-1p1@20c8110 {\n" "> -\t\t\t\t\treg = <0x20c8110>;\n" "> +\t\t\t\tregulator-1p1 {\n" "> \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -123,7 +127,7 @@ "> \t\t\t\t\tanatop-enable-bit = <0>;\n" "> \t\t\t\t};\n" "> \n" - "> -\t\t\t\tregulator-3p0 at 20c8120 {\n" + "> -\t\t\t\tregulator-3p0@20c8120 {\n" "> -\t\t\t\t\treg = <0x20c8120>;\n" "> +\t\t\t\tregulator-3p0 {\n" "> \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -133,7 +137,7 @@ "> \t\t\t\t\tanatop-enable-bit = <0>;\n" "> \t\t\t\t};\n" "> \n" - "> -\t\t\t\tregulator-2p5 at 20c8130 {\n" + "> -\t\t\t\tregulator-2p5@20c8130 {\n" "> -\t\t\t\t\treg = <0x20c8130>;\n" "> +\t\t\t\tregulator-2p5 {\n" "> \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -143,7 +147,7 @@ "> \t\t\t\t\tanatop-enable-bit = <0>;\n" "> \t\t\t\t};\n" "> \n" - "> -\t\t\t\treg_arm: regulator-vddcore at 20c8140 {\n" + "> -\t\t\t\treg_arm: regulator-vddcore@20c8140 {\n" "> -\t\t\t\t\treg = <0x20c8140>;\n" "> +\t\t\t\treg_arm: regulator-vddcore {\n" "> \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -153,7 +157,7 @@ "> \t\t\t\t\tanatop-max-voltage = <1450000>;\n" "> \t\t\t\t};\n" "> \n" - "> -\t\t\t\treg_pu: regulator-vddpu at 20c8140 {\n" + "> -\t\t\t\treg_pu: regulator-vddpu@20c8140 {\n" "> -\t\t\t\t\treg = <0x20c8140>;\n" "> +\t\t\t\treg_pu: regulator-vddpu {\n" "> \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -163,7 +167,7 @@ "> \t\t\t\t\tanatop-max-voltage = <1450000>;\n" "> \t\t\t\t};\n" "> \n" - "> -\t\t\t\treg_soc: regulator-vddsoc at 20c8140 {\n" + "> -\t\t\t\treg_soc: regulator-vddsoc@20c8140 {\n" "> -\t\t\t\t\treg = <0x20c8140>;\n" "> +\t\t\t\treg_soc: regulator-vddsoc {\n" "> \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -180,7 +184,7 @@ "> -\t\t\t\t#address-cells = <1>;\n" "> -\t\t\t\t#size-cells = <0>;\n" "> \n" - "> -\t\t\t\tregulator-1p1 at 20c8110 {\n" + "> -\t\t\t\tregulator-1p1@20c8110 {\n" "> -\t\t\t\t\treg = <0x20c8110>;\n" "> +\t\t\t\tregulator-1p1 {\n" "> \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -190,7 +194,7 @@ "> \t\t\t\t\tanatop-enable-bit = <0>;\n" "> \t\t\t\t};\n" "> \n" - "> -\t\t\t\tregulator-3p0 at 20c8120 {\n" + "> -\t\t\t\tregulator-3p0@20c8120 {\n" "> -\t\t\t\t\treg = <0x20c8120>;\n" "> +\t\t\t\tregulator-3p0 {\n" "> \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -200,7 +204,7 @@ "> \t\t\t\t\tanatop-enable-bit = <0>;\n" "> \t\t\t\t};\n" "> \n" - "> -\t\t\t\tregulator-2p5 at 20c8130 {\n" + "> -\t\t\t\tregulator-2p5@20c8130 {\n" "> -\t\t\t\t\treg = <0x20c8130>;\n" "> +\t\t\t\tregulator-2p5 {\n" "> \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -210,7 +214,7 @@ "> \t\t\t\t\tanatop-enable-bit = <0>;\n" "> \t\t\t\t};\n" "> \n" - "> -\t\t\t\treg_arm: regulator-vddcore at 20c8140 {\n" + "> -\t\t\t\treg_arm: regulator-vddcore@20c8140 {\n" "> -\t\t\t\t\treg = <0x20c8140>;\n" "> +\t\t\t\treg_arm: regulator-vddcore {\n" "> \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -220,7 +224,7 @@ "> \t\t\t\t\tanatop-max-voltage = <1450000>;\n" "> \t\t\t\t};\n" "> \n" - "> -\t\t\t\treg_pcie: regulator-vddpcie at 20c8140 {\n" + "> -\t\t\t\treg_pcie: regulator-vddpcie@20c8140 {\n" "> -\t\t\t\t\treg = <0x20c8140>;\n" "> +\t\t\t\treg_pcie: regulator-vddpcie {\n" "> \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -230,7 +234,7 @@ "> \t\t\t\t\tanatop-max-voltage = <1450000>;\n" "> \t\t\t\t};\n" "> \n" - "> -\t\t\t\treg_soc: regulator-vddsoc at 20c8140 {\n" + "> -\t\t\t\treg_soc: regulator-vddsoc@20c8140 {\n" "> -\t\t\t\t\treg = <0x20c8140>;\n" "> +\t\t\t\treg_soc: regulator-vddsoc {\n" "> \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -247,7 +251,7 @@ "> -\t\t\t\t#address-cells = <1>;\n" "> -\t\t\t\t#size-cells = <0>;\n" "> \n" - "> -\t\t\t\treg_3p0: regulator-3p0 at 20c8110 {\n" + "> -\t\t\t\treg_3p0: regulator-3p0@20c8110 {\n" "> -\t\t\t\t\treg = <0x20c8110>;\n" "> +\t\t\t\treg_3p0: regulator-3p0 {\n" "> \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -257,7 +261,7 @@ "> \t\t\t\t\tanatop-enable-bit = <0>;\n" "> \t\t\t\t};\n" "> \n" - "> -\t\t\t\treg_arm: regulator-vddcore at 20c8140 {\n" + "> -\t\t\t\treg_arm: regulator-vddcore@20c8140 {\n" "> -\t\t\t\t\treg = <0x20c8140>;\n" "> +\t\t\t\treg_arm: regulator-vddcore {\n" "> \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -267,7 +271,7 @@ "> \t\t\t\t\tanatop-max-voltage = <1450000>;\n" "> \t\t\t\t};\n" "> \n" - "> -\t\t\t\treg_soc: regulator-vddsoc at 20c8140 {\n" + "> -\t\t\t\treg_soc: regulator-vddsoc@20c8140 {\n" "> -\t\t\t\t\treg = <0x20c8140>;\n" "> +\t\t\t\treg_soc: regulator-vddsoc {\n" "> \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -284,7 +288,7 @@ "> -\t\t\t\t#address-cells = <1>;\n" "> -\t\t\t\t#size-cells = <0>;\n" "> \n" - "> -\t\t\t\treg_1p0d: regulator-vdd1p0d at 30360210 {\n" + "> -\t\t\t\treg_1p0d: regulator-vdd1p0d@30360210 {\n" "> -\t\t\t\t\treg = <0x30360210>;\n" "> +\t\t\t\treg_1p0d: regulator-vdd1p0d {\n" "> \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -294,7 +298,7 @@ "> \t\t\t\t\tanatop-enable-bit = <0>;\n" "> \t\t\t\t};\n" "> \n" - "> -\t\t\t\treg_1p2: regulator-vdd1p2 at 30360220 {\n" + "> -\t\t\t\treg_1p2: regulator-vdd1p2@30360220 {\n" "> -\t\t\t\t\treg = <0x30360220>;\n" "> +\t\t\t\treg_1p2: regulator-vdd1p2 {\n" "> \t\t\t\t\tcompatible = \"fsl,anatop-regulator\";\n" @@ -304,4 +308,4 @@ "> 2.7.4\n" > -31a23c0ed271322554e8415da41eb283f8e12fe8638885cea9ab25555ffbec27 +7d28b6c25e73eb4b9caf2f21f631fc9e6d7f646cb5bb1e1bdd55ee67e77c41db
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