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From: Borislav Petkov <bp@suse.de>
To: speck@linutronix.de
Subject: [MODERATED] Re: [patch 13/15] Hidden 13
Date: Tue, 15 May 2018 11:27:24 +0200	[thread overview]
Message-ID: <20180515092724.GA11988@pd.tnic> (raw)
In-Reply-To: <20180513140539.304778544@linutronix.de>

On Sun, May 13, 2018 at 04:01:01PM +0200, speck for Thomas Gleixner wrote:
> Subject: [patch 13/15] x86/bugs: Rework spec_ctrl base and mask logic
> From: Thomas Gleixner <tglx@linutronix.de>
> 
> x86_spec_ctrL_mask is intended to mask out bits from a MSR_SPEC_CTRL value
> which are not to be modified. Though the implementation is not really used

s/Though/However,/

> and the bitmask is inverted for no real reason. Aside of that it is missing
> the STIBP bit if it is supported by the platform, so if the mask would be
> used in x86_virt_spec_ctrl() then it would prevent a guest from setting
> STIBP.
> 
> Add the STIBP bit if supported and use the mask in x86_spec_ctrl_set_guest()
> to sanitize the value which is supplied by the guest.
> 
> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
> ---
>  arch/x86/kernel/cpu/bugs.c |   22 +++++++++++++++++-----
>  1 file changed, 17 insertions(+), 5 deletions(-)
> 
> --- a/arch/x86/kernel/cpu/bugs.c
> +++ b/arch/x86/kernel/cpu/bugs.c
> @@ -68,6 +68,10 @@ void __init check_bugs(void)
>  	if (boot_cpu_has(X86_FEATURE_MSR_SPEC_CTRL))
>  		rdmsrl(MSR_IA32_SPEC_CTRL, x86_spec_ctrl_base);
>  
> +	/* Allow STIBP in MSR_SPEC_CTRL if supported */
> +	if (boot_cpu_has(X86_FEATURE_STIBP))
> +		x86_spec_ctrl_mask |= SPEC_CTRL_STIBP;
> +
>  	/* Select the proper spectre mitigation before patching alternatives */
>  	spectre_v2_select_mitigation();
>  
> @@ -134,19 +138,27 @@ static enum spectre_v2_mitigation spectr
>  	SPECTRE_V2_NONE;
>  
>  void
> -x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool guest)
> +x86_virt_spec_ctrl(u64 guest_spec_ctrl, u64 guest_virt_spec_ctrl, bool setguest)
>  {
>  	u64 hostssbd = ssbd_tif_to_spec_ctrl(current_thread_info()->flags);
> -	u64 msr, host = x86_spec_ctrl_base;
> +	u64 msr, guest, host = x86_spec_ctrl_base;
>  
>  	/* Is MSR_SPEC_CTRL implemented ? */
>  	if (static_cpu_has(X86_FEATURE_MSR_SPEC_CTRL)) {
> +		/*
> +		 * Restrict guest_spec_ctrl to supported values. Clear the
> +		 * modifiable bits in the host base value and or the
> +		 * modifiable bits from the guest value.
> +		 */
> +		guest = host & ~x86_spec_ctrl_mask;
> +		guest |= guest_spec_ctrl & x86_spec_ctrl_mask;
> +
>  		/* SSBD controlled in MSR_SPEC_CTRL */
>  		if (static_cpu_has(X86_FEATURE_SPEC_CTRL_SSBD))
>  			host |= hostssbd;
>  
> -		if (host != guest_spec_ctrl) {
> -			msr = guest ? guest_spec_ctrl : host;
> +		if (host != guest) {
> +			msr = setguest ? guest : host;

Just a nitpick:
			msrval = setguest ? guest : host;
			wrmsrl(MSR_IA32_SPEC_CTRL, msrval);

calling it "msrval" is a bit clearer as it shows that's you're selecting
the MSR *value* and not the MSR itself. (And yes, we do select which
MSRs to access in other places).

With that

Reviewed-by: Borislav Petkov <bp@suse.de>

-- 
Regards/Gruss,
    Boris.

SUSE Linux GmbH, GF: Felix Imendörffer, Jane Smithard, Graham Norton, HRB 21284 (AG Nürnberg)
-- 

  reply	other threads:[~2018-05-15  9:27 UTC|newest]

Thread overview: 57+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-13 14:00 [patch 00/15] Hidden 0 Thomas Gleixner
2018-05-13 14:00 ` [patch 01/15] Hidden 1 Thomas Gleixner
2018-05-13 22:17   ` [MODERATED] " Borislav Petkov
2018-05-15  9:30   ` Paolo Bonzini
2018-05-16  2:32   ` Konrad Rzeszutek Wilk
2018-05-16  7:51     ` Thomas Gleixner
2018-05-13 14:00 ` [patch 02/15] Hidden 2 Thomas Gleixner
2018-05-16  2:39   ` [MODERATED] " Konrad Rzeszutek Wilk
2018-05-13 14:00 ` [patch 03/15] Hidden 3 Thomas Gleixner
2018-05-14 10:02   ` [MODERATED] " Borislav Petkov
2018-05-16  2:49   ` Konrad Rzeszutek Wilk
2018-05-16  8:07     ` Thomas Gleixner
2018-05-16  8:53       ` [MODERATED] Re: " Borislav Petkov
2018-05-13 14:00 ` [patch 04/15] Hidden 4 Thomas Gleixner
2018-05-14 11:11   ` [MODERATED] " Borislav Petkov
2018-05-16  2:53   ` Konrad Rzeszutek Wilk
2018-05-13 14:00 ` [patch 05/15] Hidden 5 Thomas Gleixner
2018-05-14 11:18   ` [MODERATED] " Borislav Petkov
2018-05-16  3:24   ` Konrad Rzeszutek Wilk
2018-05-16  9:09     ` Thomas Gleixner
2018-05-13 14:00 ` [patch 06/15] Hidden 6 Thomas Gleixner
2018-05-14 12:01   ` [MODERATED] " Borislav Petkov
2018-05-14 12:09   ` Peter Zijlstra
2018-05-14 12:46     ` Thomas Gleixner
2018-05-16  3:15   ` [MODERATED] " Konrad Rzeszutek Wilk
2018-05-16  8:44     ` Thomas Gleixner
2018-05-13 14:00 ` [patch 07/15] Hidden 7 Thomas Gleixner
2018-05-14 17:07   ` [MODERATED] " Borislav Petkov
2018-05-16  3:22   ` Konrad Rzeszutek Wilk
2018-05-16  8:46     ` Thomas Gleixner
2018-05-16 12:15       ` Thomas Gleixner
2018-05-13 14:00 ` [patch 08/15] Hidden 8 Thomas Gleixner
2018-05-14 17:58   ` [MODERATED] " Borislav Petkov
2018-05-16  3:31   ` Konrad Rzeszutek Wilk
2018-05-16 12:22     ` Thomas Gleixner
2018-05-16 13:48       ` [MODERATED] " Konrad Rzeszutek Wilk
2018-05-13 14:00 ` [patch 09/15] Hidden 9 Thomas Gleixner
2018-05-14 19:49   ` [MODERATED] " Borislav Petkov
2018-05-13 14:00 ` [patch 10/15] Hidden 10 Thomas Gleixner
2018-05-16  3:38   ` [MODERATED] " Konrad Rzeszutek Wilk
2018-05-16  8:51     ` Thomas Gleixner
2018-05-13 14:00 ` [patch 11/15] Hidden 11 Thomas Gleixner
2018-05-14 20:02   ` [MODERATED] " Borislav Petkov
2018-05-16  3:35   ` Konrad Rzeszutek Wilk
2018-05-16  8:50     ` Thomas Gleixner
2018-05-13 14:01 ` [patch 12/15] Hidden 12 Thomas Gleixner
2018-05-14 20:18   ` [MODERATED] " Borislav Petkov
2018-05-16  3:40   ` Konrad Rzeszutek Wilk
2018-05-13 14:01 ` [patch 13/15] Hidden 13 Thomas Gleixner
2018-05-15  9:27   ` Borislav Petkov [this message]
2018-05-16  3:42   ` [MODERATED] " Konrad Rzeszutek Wilk
2018-05-16  8:56     ` Thomas Gleixner
2018-05-13 14:01 ` [patch 14/15] Hidden 14 Thomas Gleixner
2018-05-15 15:35   ` [MODERATED] " Borislav Petkov
2018-05-16  3:44   ` Konrad Rzeszutek Wilk
2018-05-13 14:01 ` [patch 15/15] Hidden 15 Thomas Gleixner
2018-05-13 14:22 ` [patch 00/15] Hidden 0 Thomas Gleixner

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