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Date: Tue, 15 May 2018 22:53:42 -0400
From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
Subject: [MODERATED] Re: [patch 04/15] Hidden 4
Message-ID: <20180516025342.GE18660@char.us.oracle.com>
References: <20180513140048.543641807@linutronix.de>
 <20180513140538.551893231@linutronix.de>
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To: speck@linutronix.de
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On Sun, May 13, 2018 at 04:00:52PM +0200, speck for Thomas Gleixner wrote:
> Subject: [patch 04/15] x86/cpufeatures: Disentangle SSBD enumeration
> From: Thomas Gleixner <tglx@linutronix.de>
> 
> The SSBD enumeration is similarly to the other bits magically shared
> between Intel and AMD though the mechanisms are different.
> 
> Make X86_FEATURE_SSBD synthetic and set it depending on the vendor specific
> features or family dependent setup.
> 
> Change the Intel bit to X86_FEATURE_SPEC_CTRL_SSBD to denote that SSBD is
> controlled via MSR_SPEC_CTRL and fix up the usage sites.

I think you are missing the clearing of the X86_FEATURE_SPEC_CTRL_SSBD in
early_init_intel when we detect the microcode is busted?