From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from aserp2130.oracle.com ([141.146.126.79]) by Galois.linutronix.de with esmtps (TLS1.2:RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1fIn3m-0003UJ-G8 for speck@linutronix.de; Wed, 16 May 2018 05:25:03 +0200 Received: from pps.filterd (aserp2130.oracle.com [127.0.0.1]) by aserp2130.oracle.com (8.16.0.22/8.16.0.22) with SMTP id w4G3L5At089647 for ; Wed, 16 May 2018 03:24:54 GMT Received: from userv0021.oracle.com (userv0021.oracle.com [156.151.31.71]) by aserp2130.oracle.com with ESMTP id 2hxpvcshg2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Wed, 16 May 2018 03:24:54 +0000 Received: from userv0121.oracle.com (userv0121.oracle.com [156.151.31.72]) by userv0021.oracle.com (8.14.4/8.14.4) with ESMTP id w4G3Or2D024694 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Wed, 16 May 2018 03:24:53 GMT Received: from abhmp0001.oracle.com (abhmp0001.oracle.com [141.146.116.7]) by userv0121.oracle.com (8.14.4/8.13.8) with ESMTP id w4G3Orj5018652 for ; Wed, 16 May 2018 03:24:53 GMT Date: Tue, 15 May 2018 23:24:52 -0400 From: Konrad Rzeszutek Wilk Subject: [MODERATED] Re: [patch 05/15] Hidden 5 Message-ID: <20180516032452.GH18660@char.us.oracle.com> References: <20180513140048.543641807@linutronix.de> <20180513140538.633132990@linutronix.de> MIME-Version: 1.0 In-Reply-To: <20180513140538.633132990@linutronix.de> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Sun, May 13, 2018 at 04:00:53PM +0200, speck for Thomas Gleixner wrote: > Subject: [patch 05/15] x86/cpufeatures: Add FEATURE_ZEN > From: Thomas Gleixner > > Add a ZEN feature bit so family-dependent static_cpu_has() optimizations > can be built for ZEN. .. In the future this may cover other architectures as well. Would it make sense to call this something more generic? Say X86_FEATURE_SSBD_SYNC_SMT ? > > Signed-off-by: Thomas Gleixner > --- > arch/x86/include/asm/cpufeatures.h | 1 + > arch/x86/kernel/cpu/amd.c | 1 + > 2 files changed, 2 insertions(+) > > --- a/arch/x86/include/asm/cpufeatures.h > +++ b/arch/x86/include/asm/cpufeatures.h > @@ -218,6 +218,7 @@ > #define X86_FEATURE_IBRS ( 7*32+25) /* Indirect Branch Restricted Speculation */ > #define X86_FEATURE_IBPB ( 7*32+26) /* Indirect Branch Prediction Barrier */ > #define X86_FEATURE_STIBP ( 7*32+27) /* Single Thread Indirect Branch Predictors */ > +#define X86_FEATURE_ZEN ( 7*32+28) /* "" CPU is AMD family 0x17 (Zen) */ > > /* Virtualization flags: Linux defined, word 8 */ > #define X86_FEATURE_TPR_SHADOW ( 8*32+ 0) /* Intel TPR Shadow */ > --- a/arch/x86/kernel/cpu/amd.c > +++ b/arch/x86/kernel/cpu/amd.c > @@ -812,6 +812,7 @@ static void init_amd_bd(struct cpuinfo_x > > static void init_amd_zn(struct cpuinfo_x86 *c) > { > + set_cpu_cap(c, X86_FEATURE_ZEN); > /* > * Fix erratum 1076: CPB feature bit not being set in CPUID. It affects > * all up to and including B1. >