From mboxrd@z Thu Jan 1 00:00:00 1970 Return-path: Received: from aserp2120.oracle.com ([141.146.126.78]) by Galois.linutronix.de with esmtps (TLS1.2:RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1fInMN-0003jz-Qb for speck@linutronix.de; Wed, 16 May 2018 05:44:17 +0200 Received: from pps.filterd (aserp2120.oracle.com [127.0.0.1]) by aserp2120.oracle.com (8.16.0.22/8.16.0.22) with SMTP id w4G3fXum032659 for ; Wed, 16 May 2018 03:44:09 GMT Received: from userv0022.oracle.com (userv0022.oracle.com [156.151.31.74]) by aserp2120.oracle.com with ESMTP id 2hx29w2wj9-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Wed, 16 May 2018 03:44:08 +0000 Received: from aserv0121.oracle.com (aserv0121.oracle.com [141.146.126.235]) by userv0022.oracle.com (8.14.4/8.14.4) with ESMTP id w4G3i7si030759 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Wed, 16 May 2018 03:44:07 GMT Received: from abhmp0003.oracle.com (abhmp0003.oracle.com [141.146.116.9]) by aserv0121.oracle.com (8.14.4/8.13.8) with ESMTP id w4G3i75d004147 for ; Wed, 16 May 2018 03:44:07 GMT Date: Tue, 15 May 2018 23:44:06 -0400 From: Konrad Rzeszutek Wilk Subject: [MODERATED] Re: [patch 14/15] Hidden 14 Message-ID: <20180516034406.GE26939@char.us.oracle.com> References: <20180513140048.543641807@linutronix.de> <20180513140539.386248263@linutronix.de> MIME-Version: 1.0 In-Reply-To: <20180513140539.386248263@linutronix.de> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Sun, May 13, 2018 at 04:01:02PM +0200, speck for Thomas Gleixner wrote: > Subject: [patch 14/15] x86/speculation, KVM: Implement support for VIRT_SPEC_CTRL/LS_CFG > From: Thomas Gleixner > > Add the necessary logic for supporting the emulated VIRT_SPEC_CTRL MSR to > x86_virt_spec_ctrl(). If either X86_FEATURE_LS_CFG_SSBD or > X86_FEATURE_VIRT_SPEC_CTRL is set then use the new guest_virt_spec_ctrl > argument to check whether the state must be modified on the host. The > update reuses speculative_store_bypass_update() so the ZEN-specific sibling > coordination can be reused. > > Signed-off-by: Thomas Gleixner > --- > arch/x86/include/asm/spec-ctrl.h | 6 ++++++ > arch/x86/kernel/cpu/bugs.c | 24 ++++++++++++++++++++++++ > 2 files changed, 30 insertions(+) > > --- a/arch/x86/include/asm/spec-ctrl.h > +++ b/arch/x86/include/asm/spec-ctrl.h > @@ -56,6 +56,12 @@ static inline u64 ssbd_tif_to_spec_ctrl( > return (tifn & _TIF_SSBD) >> (TIF_SSBD - SPEC_CTRL_SSBD_SHIFT); > } > > +static inline unsigned long ssbd_spec_ctrl_to_tif(u64 spec_ctrl) > +{ > + BUILD_BUG_ON(TIF_SSBD < SPEC_CTRL_SSBD_SHIFT); > + return (spec_ctrl & SPEC_CTRL_SSBD) << (TIF_SSBD - SPEC_CTRL_SSBD_SHIFT); > +} > + > static inline u64 ssbd_tif_to_amd_ls_cfg(u64 tifn) > { > return (tifn & _TIF_SSBD) ? x86_amd_ls_cfg_ssbd_mask : 0ULL; > --- a/arch/x86/kernel/cpu/bugs.c > +++ b/arch/x86/kernel/cpu/bugs.c > @@ -162,6 +162,30 @@ x86_virt_spec_ctrl(u64 guest_spec_ctrl, > wrmsrl(MSR_IA32_SPEC_CTRL, msr); > } > } > + > + /* > + * If SSBD is not handled in MSR_SPEC_CTRL on AMD update s/AMD/AMD,/ > + * MSR_AMD64_L2_CFG or MSR_VIRT_SPEC_CTRL if supported. > + */ > + if (!static_cpu_has(X86_FEATURE_LS_CFG_SSBD) && > + !static_cpu_has(X86_FEATURE_VIRT_SSBD)) > + return; > + > + /* If host has SSBD disabled via command line, force it */ > + if (static_cpu_has(X86_FEATURE_SPEC_STORE_BYPASS_DISABLE)) > + hostssbd |= SPEC_CTRL_SSBD; > + > + /* Sanitize the guest value */ > + guest = guest_virt_spec_ctrl & SPEC_CTRL_SSBD; > + > + if (hostssbd != guest) { > + unsigned long tif; > + > + tif = setguest ? ssbd_spec_ctrl_to_tif(guest) : > + ssbd_spec_ctrl_to_tif(hostssbd); > + > + speculative_store_bypass_update(tif); > + } > } > EXPORT_SYMBOL_GPL(x86_virt_spec_ctrl); > >