diff for duplicates of <20180517162555.00002bd3@huawei.com> diff --git a/a/1.txt b/N1/1.txt index c6fb630..91c711a 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,5 +1,5 @@ On Fri, 11 May 2018 20:06:08 +0100 -Jean-Philippe Brucker <jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org> wrote: +Jean-Philippe Brucker <jean-philippe.brucker@arm.com> wrote: > Some systems allow devices to handle I/O Page Faults in the core mm. For > example systems implementing the PCI PRI extension or Arm SMMU stall @@ -23,7 +23,7 @@ Jean-Philippe Brucker <jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org> wrote > about ordering between calls to iopf_queue_add_device() and > iommu_register_device_fault_handler(). > -> Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org> +> Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com> Hi Jean-Phillipe, diff --git a/a/content_digest b/N1/content_digest index 958c3b8..f00b174 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,31 +1,46 @@ "ref\020180511190641.23008-1-jean-philippe.brucker@arm.com\0" "ref\020180511190641.23008-8-jean-philippe.brucker@arm.com\0" - "ref\020180511190641.23008-8-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org\0" - "From\0Jonathan Cameron <Jonathan.Cameron-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>\0" + "From\0Jonathan Cameron <Jonathan.Cameron@huawei.com>\0" "Subject\0Re: [PATCH v2 07/40] iommu: Add a page fault handler\0" "Date\0Thu, 17 May 2018 16:25:55 +0100\0" - "To\0Jean-Philippe Brucker <jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>\0" - "Cc\0kvm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" - linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - xuzaibo-hv44wF8Li93QT0dZR+AlfA@public.gmane.org - will.deacon-5wv7dgnIgG8@public.gmane.org - okaya-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org - linux-mm-Bw31MaZKKs3YtjvyW6yDsg@public.gmane.org - ashok.raj-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org - bharatku-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org - linux-acpi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - rfranz-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org - devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - rgummal-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org - linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org - dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org - ilias.apalodimas-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org - iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org - " christian.koenig-5C7GfCeVMHo@public.gmane.org\0" + "To\0Jean-Philippe Brucker <jean-philippe.brucker@arm.com>\0" + "Cc\0<linux-arm-kernel@lists.infradead.org>" + <linux-pci@vger.kernel.org> + <linux-acpi@vger.kernel.org> + <devicetree@vger.kernel.org> + <iommu@lists.linux-foundation.org> + <kvm@vger.kernel.org> + <linux-mm@kvack.org> + <joro@8bytes.org> + <will.deacon@arm.com> + <robin.murphy@arm.com> + <alex.williamson@redhat.com> + <tn@semihalf.com> + <liubo95@huawei.com> + <thunder.leizhen@huawei.com> + <xieyisheng1@huawei.com> + <xuzaibo@huawei.com> + <ilias.apalodimas@linaro.org> + <liudongdong3@huawei.com> + <shunyong.yang@hxt-semitech.com> + <nwatters@codeaurora.org> + <okaya@codeaurora.org> + <jcrouse@codeaurora.org> + <rfranz@cavium.com> + <dwmw2@infradead.org> + <jacob.jun.pan@linux.intel.com> + <yi.l.liu@intel.com> + <ashok.raj@intel.com> + <kevin.tian@intel.com> + <baolu.lu@linux.intel.com> + <robdclark@gmail.com> + <christian.koenig@amd.com> + <bharatku@xilinx.com> + " <rgummal@xilinx.com>\0" "\00:1\0" "b\0" "On Fri, 11 May 2018 20:06:08 +0100\n" - "Jean-Philippe Brucker <jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org> wrote:\n" + "Jean-Philippe Brucker <jean-philippe.brucker@arm.com> wrote:\n" "\n" "> Some systems allow devices to handle I/O Page Faults in the core mm. For\n" "> example systems implementing the PCI PRI extension or Arm SMMU stall\n" @@ -49,7 +64,7 @@ "> about ordering between calls to iopf_queue_add_device() and\n" "> iommu_register_device_fault_handler().\n" "> \n" - "> Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>\n" + "> Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>\n" "\n" "Hi Jean-Phillipe,\n" "\n" @@ -567,4 +582,4 @@ "> +\n" > #endif /* __LINUX_IOMMU_H */ -4e1f28de23e1c056221f17239ea96df8dd3478691b0236e623f8c5e4d78e02b8 +ca70da9dcffb06edb978597ba448be7d4af9e575b8ac40ed1005d1b58ec10341
diff --git a/a/1.txt b/N2/1.txt index c6fb630..91c711a 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,5 +1,5 @@ On Fri, 11 May 2018 20:06:08 +0100 -Jean-Philippe Brucker <jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org> wrote: +Jean-Philippe Brucker <jean-philippe.brucker@arm.com> wrote: > Some systems allow devices to handle I/O Page Faults in the core mm. For > example systems implementing the PCI PRI extension or Arm SMMU stall @@ -23,7 +23,7 @@ Jean-Philippe Brucker <jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org> wrote > about ordering between calls to iopf_queue_add_device() and > iommu_register_device_fault_handler(). > -> Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org> +> Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com> Hi Jean-Phillipe, diff --git a/a/content_digest b/N2/content_digest index 958c3b8..f41ebab 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,31 +1,13 @@ "ref\020180511190641.23008-1-jean-philippe.brucker@arm.com\0" "ref\020180511190641.23008-8-jean-philippe.brucker@arm.com\0" - "ref\020180511190641.23008-8-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org\0" - "From\0Jonathan Cameron <Jonathan.Cameron-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>\0" - "Subject\0Re: [PATCH v2 07/40] iommu: Add a page fault handler\0" + "From\0Jonathan.Cameron@huawei.com (Jonathan Cameron)\0" + "Subject\0[PATCH v2 07/40] iommu: Add a page fault handler\0" "Date\0Thu, 17 May 2018 16:25:55 +0100\0" - "To\0Jean-Philippe Brucker <jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>\0" - "Cc\0kvm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" - linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - xuzaibo-hv44wF8Li93QT0dZR+AlfA@public.gmane.org - will.deacon-5wv7dgnIgG8@public.gmane.org - okaya-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org - linux-mm-Bw31MaZKKs3YtjvyW6yDsg@public.gmane.org - ashok.raj-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org - bharatku-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org - linux-acpi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - rfranz-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org - devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - rgummal-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org - linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org - dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org - ilias.apalodimas-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org - iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org - " christian.koenig-5C7GfCeVMHo@public.gmane.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "On Fri, 11 May 2018 20:06:08 +0100\n" - "Jean-Philippe Brucker <jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org> wrote:\n" + "Jean-Philippe Brucker <jean-philippe.brucker@arm.com> wrote:\n" "\n" "> Some systems allow devices to handle I/O Page Faults in the core mm. For\n" "> example systems implementing the PCI PRI extension or Arm SMMU stall\n" @@ -49,7 +31,7 @@ "> about ordering between calls to iopf_queue_add_device() and\n" "> iommu_register_device_fault_handler().\n" "> \n" - "> Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>\n" + "> Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>\n" "\n" "Hi Jean-Phillipe,\n" "\n" @@ -567,4 +549,4 @@ "> +\n" > #endif /* __LINUX_IOMMU_H */ -4e1f28de23e1c056221f17239ea96df8dd3478691b0236e623f8c5e4d78e02b8 +16dd8fb7767ca5d58a402092f9d21156435f69e0ae5eddf1721c8c254f35e51d
diff --git a/a/1.txt b/N3/1.txt index c6fb630..91c711a 100644 --- a/a/1.txt +++ b/N3/1.txt @@ -1,5 +1,5 @@ On Fri, 11 May 2018 20:06:08 +0100 -Jean-Philippe Brucker <jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org> wrote: +Jean-Philippe Brucker <jean-philippe.brucker@arm.com> wrote: > Some systems allow devices to handle I/O Page Faults in the core mm. For > example systems implementing the PCI PRI extension or Arm SMMU stall @@ -23,7 +23,7 @@ Jean-Philippe Brucker <jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org> wrote > about ordering between calls to iopf_queue_add_device() and > iommu_register_device_fault_handler(). > -> Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org> +> Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com> Hi Jean-Phillipe, diff --git a/a/content_digest b/N3/content_digest index 958c3b8..1823d0f 100644 --- a/a/content_digest +++ b/N3/content_digest @@ -1,31 +1,46 @@ "ref\020180511190641.23008-1-jean-philippe.brucker@arm.com\0" "ref\020180511190641.23008-8-jean-philippe.brucker@arm.com\0" - "ref\020180511190641.23008-8-jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org\0" - "From\0Jonathan Cameron <Jonathan.Cameron-hv44wF8Li93QT0dZR+AlfA@public.gmane.org>\0" + "From\0Jonathan Cameron <Jonathan.Cameron@huawei.com>\0" "Subject\0Re: [PATCH v2 07/40] iommu: Add a page fault handler\0" "Date\0Thu, 17 May 2018 16:25:55 +0100\0" - "To\0Jean-Philippe Brucker <jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>\0" - "Cc\0kvm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" - linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - xuzaibo-hv44wF8Li93QT0dZR+AlfA@public.gmane.org - will.deacon-5wv7dgnIgG8@public.gmane.org - okaya-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org - linux-mm-Bw31MaZKKs3YtjvyW6yDsg@public.gmane.org - ashok.raj-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org - bharatku-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org - linux-acpi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - rfranz-YGCgFSpz5w/QT0dZR+AlfA@public.gmane.org - devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org - rgummal-gjFFaj9aHVfQT0dZR+AlfA@public.gmane.org - linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org - dwmw2-wEGCiKHe2LqWVfeAwA7xHQ@public.gmane.org - ilias.apalodimas-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org - iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org - " christian.koenig-5C7GfCeVMHo@public.gmane.org\0" + "To\0Jean-Philippe Brucker <jean-philippe.brucker@arm.com>\0" + "Cc\0linux-arm-kernel@lists.infradead.org" + linux-pci@vger.kernel.org + linux-acpi@vger.kernel.org + devicetree@vger.kernel.org + iommu@lists.linux-foundation.org + kvm@vger.kernel.org + linux-mm@kvack.org + joro@8bytes.org + will.deacon@arm.com + robin.murphy@arm.com + alex.williamson@redhat.com + tn@semihalf.com + liubo95@huawei.com + thunder.leizhen@huawei.com + xieyisheng1@huawei.com + xuzaibo@huawei.com + ilias.apalodimas@linaro.org + liudongdong3@huawei.com + shunyong.yang@hxt-semitech.com + nwatters@codeaurora.org + okaya@codeaurora.org + jcrouse@codeaurora.org + rfranz@cavium.com + dwmw2@infradead.org + jacob.jun.pan@linux.intel.com + yi.l.liu@intel.com + ashok.raj@intel.com + kevin.tian@intel.com + baolu.lu@linux.intel.com + robdclark@gmail.com + christian.koenig@amd.com + bharatku@xilinx.com + " rgummal@xilinx.com\0" "\00:1\0" "b\0" "On Fri, 11 May 2018 20:06:08 +0100\n" - "Jean-Philippe Brucker <jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org> wrote:\n" + "Jean-Philippe Brucker <jean-philippe.brucker@arm.com> wrote:\n" "\n" "> Some systems allow devices to handle I/O Page Faults in the core mm. For\n" "> example systems implementing the PCI PRI extension or Arm SMMU stall\n" @@ -49,7 +64,7 @@ "> about ordering between calls to iopf_queue_add_device() and\n" "> iommu_register_device_fault_handler().\n" "> \n" - "> Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker-5wv7dgnIgG8@public.gmane.org>\n" + "> Signed-off-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com>\n" "\n" "Hi Jean-Phillipe,\n" "\n" @@ -567,4 +582,4 @@ "> +\n" > #endif /* __LINUX_IOMMU_H */ -4e1f28de23e1c056221f17239ea96df8dd3478691b0236e623f8c5e4d78e02b8 +8073bff3d9f576229a567dca411bdf299e81f60c9aafd997e9508cad90066d21
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