From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: [v5,3/6] dt-bindings: fsl-qdma: Add NXP Layerscpae qDMA controller bindings From: Wen He Message-Id: <20180525111920.24498-3-wen.he_1@nxp.com> Date: Fri, 25 May 2018 19:19:17 +0800 To: vkoul@kernel.org, dmaengine@vger.kernel.org Cc: robh+dt@kernel.org, devicetree@vger.kernel.org, leoyang.li@nxp.com, jiafei.pan@nxp.com, jiaheng.fan@nxp.com, wen.he_1@nxp.com List-ID: RG9jdW1lbnQgdGhlIGRldmljZXRyZWUgYmluZGluZ3MgZm9yIE5YUCBMYXllcnNjYXBlIHFETUEg Y29udHJvbGxlcgp3aGljaCBjb3VsZCBiZSBmb3VuZCBvbiBOWFAgUW9ySVEgTGF5ZXJzY2FwZSBT b0NzLgoKU2lnbmVkLW9mZi1ieTogV2VuIEhlIDx3ZW4uaGVfMUBueHAuY29tPgotLS0KY2hhbmdl IGluIHY1OgoJLSBSZXBsYWNlIGR0cyBub2RlIHZhcmlhYmxlICdxdWV1ZXMnIHRvICdmc2wscXVl dWVzJyB0aGF0IGFkZCB2ZW5kb3IgcHJlZml4CgpjaGFuZ2UgaW4gdjQ6CgktIFJld3JpdGUgdGhl IGJpbmRpbmdzIGRvY3VtZW50IHRoYXQgZm9sbG93cyBnZW5lcmljIERNQSBiaW5kaW5ncyBmaWxl CgpjaGFuZ2UgaW4gdjM6CgktIG5vIGNoYW5nZQoKY2hhbmdlIGluIHYyOgoJLSBSZW1vdmUgaW5k ZW50YXRpb24KCS0gQWRkICJTaG91bGQgYmUiIGJlZm9yZSAnZnNsLGxzMTAyMWEtcWRtYScKCS0g UmVwbGFjZSAnY2hhbm5lbHMnIGJ5ICdkbWEtY2hhbm5lbHMnCgktIFJlcGxhY2UgJ3FkbWFAODM5 MDAwMCcgYnkgJ2RtYS1jb250cm9sbGVyQDgzOTAwMDAnCgogRG9jdW1lbnRhdGlvbi9kZXZpY2V0 cmVlL2JpbmRpbmdzL2RtYS9mc2wtcWRtYS50eHQgfCAgIDQxICsrKysrKysrKysrKysrKysrKysr CiAxIGZpbGVzIGNoYW5nZWQsIDQxIGluc2VydGlvbnMoKyksIDAgZGVsZXRpb25zKC0pCiBjcmVh dGUgbW9kZSAxMDA2NDQgRG9jdW1lbnRhdGlvbi9kZXZpY2V0cmVlL2JpbmRpbmdzL2RtYS9mc2wt cWRtYS50eHQKCmRpZmYgLS1naXQgYS9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3Mv ZG1hL2ZzbC1xZG1hLnR4dCBiL0RvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9kbWEv ZnNsLXFkbWEudHh0Cm5ldyBmaWxlIG1vZGUgMTAwNjQ0CmluZGV4IDAwMDAwMDAuLjk5YjNkNzQK LS0tIC9kZXYvbnVsbAorKysgYi9Eb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvZG1h L2ZzbC1xZG1hLnR4dApAQCAtMCwwICsxLDQxIEBACitOWFAgTGF5ZXJzY2FwZSBTb0MgcURNQSBD b250cm9sbGVyCis9PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09PT09CisKK1RoaXMgZGV2 aWNlIGZvbGxvd3MgdGhlIGdlbmVyaWMgRE1BIGJpbmRpbmdzIGRlZmluZWQgaW4gZG1hL2RtYS50 eHQuCisKK1JlcXVpcmVkIHByb3BlcnRpZXM6CisKKy0gY29tcGF0aWJsZToJCU11c3QgYmUgb25l IG9mCisJCQkgImZzbCxsczEwMjFhLXFkbWEiOiBmb3IgTFMxMDIxQSBCb2FyZAorCQkJICJmc2ws bHMxMDQzYS1xZG1hIjogZm9yIGxzMTA0M0EgQm9hcmQKKwkJCSAiZnNsLGxzMTA0NmEtcWRtYSI6 IGZvciBsczEwNDZBIEJvYXJkCistIHJlZzoJCQlTaG91bGQgY29udGFpbiB0aGUgcmVnaXN0ZXIn cyBiYXNlIGFkZHJlc3MgYW5kIGxlbmd0aC4KKy0gaW50ZXJydXB0czoJCVNob3VsZCBjb250YWlu IGEgcmVmZXJlbmNlIHRvIHRoZSBpbnRlcnJ1cHQgdXNlZCBieSB0aGlzCisJCQlkZXZpY2UuCist IGludGVycnVwdC1uYW1lczoJU2hvdWxkIGNvbnRhaW4gaW50ZXJydXB0IG5hbWVzOgorCQkJICJx ZG1hLWVycm9yIjogdGhlIGVycm9yIGludGVycnVwdAorCQkJICJxZG1hLXF1ZXVlIjogdGhlIHF1 ZXVlIGludGVycnVwdAorLSBmc2wscXVldWVzOgkJU2hvdWxkIGNvbnRhaW4gbnVtYmVyIG9mIHF1 ZXVlcyBzdXBwb3J0ZWQuCisKK09wdGlvbmFsIHByb3BlcnRpZXM6CisKKy0gZG1hLWNoYW5uZWxz OgkJTnVtYmVyIG9mIERNQSBjaGFubmVscyBzdXBwb3J0ZWQgYnkgdGhlIGNvbnRyb2xsZXIuCist IGJpZy1lbmRpYW46CQlJZiBwcmVzZW50IHJlZ2lzdGVycyBhbmQgaGFyZHdhcmUgc2NhdHRlci9n YXRoZXIgZGVzY3JpcHRvcnMKKwkJCW9mIHRoZSBxRE1BIGFyZSBpbXBsZW1lbnRlZCBpbiBiaWcg ZW5kaWFuIG1vZGUsIG90aGVyd2lzZSBpbiBsaXR0bGUKKwkJCW1vZGUuCisKK0V4YW1wbGVzOgor CisJcWRtYTogZG1hLWNvbnRyb2xsZXJAODM5MDAwMCB7CisJCWNvbXBhdGlibGUgPSAiZnNsLGxz MTAyMWEtcWRtYSI7CisJCXJlZyA9IDwweDAgMHg4Mzk4MDAwIDB4MCAweDIwMDAgLyogQ29udHJv bGxlciByZWdpc3RlcnMgKi8KKwkJICAgICAgIDB4MCAweDgzOWEwMDAgMHgwIDB4MjAwMD47IC8q IEJsb2NrIHJlZ2lzdGVycyAqLworCQlpbnRlcnJ1cHRzID0gPEdJQ19TUEkgMTg1IElSUV9UWVBF X0xFVkVMX0hJR0g+LAorCQkJCTxHSUNfU1BJIDc2IElSUV9UWVBFX0xFVkVMX0hJR0g+OworCQlp bnRlcnJ1cHQtbmFtZXMgPSAicWRtYS1lcnJvciIsICJxZG1hLXF1ZXVlIjsKKwkJZG1hLWNoYW5u ZWxzID0gPDg+OworCQlxdWV1ZXMgPSA8Mj47CisJCWJpZy1lbmRpYW47CisJfTsKKworRE1BIGNs aWVudHMgbXVzdCB1c2UgdGhlIGZvcm1hdCBkZXNjcmliZWQgaW4gZG1hL2RtYS50eHQgZmlsZS4K From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: From: Wen He Subject: [v5 3/6] dt-bindings: fsl-qdma: Add NXP Layerscpae qDMA controller bindings Date: Fri, 25 May 2018 19:19:17 +0800 Message-ID: <20180525111920.24498-3-wen.he_1@nxp.com> In-Reply-To: <20180525111920.24498-1-wen.he_1@nxp.com> References: <20180525111920.24498-1-wen.he_1@nxp.com> MIME-Version: 1.0 Content-Type: text/plain To: vkoul@kernel.org, dmaengine@vger.kernel.org Cc: robh+dt@kernel.org, devicetree@vger.kernel.org, leoyang.li@nxp.com, jiafei.pan@nxp.com, jiaheng.fan@nxp.com, wen.he_1@nxp.com List-ID: Document the devicetree bindings for NXP Layerscape qDMA controller which could be found on NXP QorIQ Layerscape SoCs. Signed-off-by: Wen He --- change in v5: - Replace dts node variable 'queues' to 'fsl,queues' that add vendor prefix change in v4: - Rewrite the bindings document that follows generic DMA bindings file change in v3: - no change change in v2: - Remove indentation - Add "Should be" before 'fsl,ls1021a-qdma' - Replace 'channels' by 'dma-channels' - Replace 'qdma@8390000' by 'dma-controller@8390000' Documentation/devicetree/bindings/dma/fsl-qdma.txt | 41 ++++++++++++++++++++ 1 files changed, 41 insertions(+), 0 deletions(-) create mode 100644 Documentation/devicetree/bindings/dma/fsl-qdma.txt diff --git a/Documentation/devicetree/bindings/dma/fsl-qdma.txt b/Documentation/devicetree/bindings/dma/fsl-qdma.txt new file mode 100644 index 0000000..99b3d74 --- /dev/null +++ b/Documentation/devicetree/bindings/dma/fsl-qdma.txt @@ -0,0 +1,41 @@ +NXP Layerscape SoC qDMA Controller +================================== + +This device follows the generic DMA bindings defined in dma/dma.txt. + +Required properties: + +- compatible: Must be one of + "fsl,ls1021a-qdma": for LS1021A Board + "fsl,ls1043a-qdma": for ls1043A Board + "fsl,ls1046a-qdma": for ls1046A Board +- reg: Should contain the register's base address and length. +- interrupts: Should contain a reference to the interrupt used by this + device. +- interrupt-names: Should contain interrupt names: + "qdma-error": the error interrupt + "qdma-queue": the queue interrupt +- fsl,queues: Should contain number of queues supported. + +Optional properties: + +- dma-channels: Number of DMA channels supported by the controller. +- big-endian: If present registers and hardware scatter/gather descriptors + of the qDMA are implemented in big endian mode, otherwise in little + mode. + +Examples: + + qdma: dma-controller@8390000 { + compatible = "fsl,ls1021a-qdma"; + reg = <0x0 0x8398000 0x0 0x2000 /* Controller registers */ + 0x0 0x839a000 0x0 0x2000>; /* Block registers */ + interrupts = , + ; + interrupt-names = "qdma-error", "qdma-queue"; + dma-channels = <8>; + queues = <2>; + big-endian; + }; + +DMA clients must use the format described in dma/dma.txt file. -- 1.7.1