From: Jonathan Cameron <jic23@jic23.retrosnub.co.uk>
To: Jean-Baptiste Maneyrol <jmaneyrol@invensense.com>
Cc: linux-iio@vger.kernel.org
Subject: Re: [PATCH v2 4/5] iio: imu: inv_mpu6050: better fifo overflow handling
Date: Sun, 27 May 2018 11:06:29 +0100 [thread overview]
Message-ID: <20180527110629.07fa7c17@archlinux> (raw)
In-Reply-To: <20180522141822.11598-4-jmaneyrol@invensense.com>
On Tue, 22 May 2018 16:18:21 +0200
Jean-Baptiste Maneyrol <jmaneyrol@invensense.com> wrote:
> Use fifo overflow bit from int status rather than using an
> arbitrary threshold.
>
> Signed-off-by: Jean-Baptiste Maneyrol <jmaneyrol@invensense.com>
Applied,
Thanks,
Jonathan
> ---
> drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h | 2 +-
> drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c | 5 +++--
> 2 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h b/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h
> index a1130b9a420c..6bc80ac9d120 100644
> --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h
> +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_iio.h
> @@ -166,6 +166,7 @@ struct inv_mpu6050_state {
> #define INV_MPU6050_REG_RAW_GYRO 0x43
>
> #define INV_MPU6050_REG_INT_STATUS 0x3A
> +#define INV_MPU6050_BIT_FIFO_OVERFLOW_INT 0x10
> #define INV_MPU6050_BIT_RAW_DATA_RDY_INT 0x01
>
> #define INV_MPU6050_REG_USER_CTRL 0x6A
> @@ -190,7 +191,6 @@ struct inv_mpu6050_state {
>
> #define INV_MPU6050_BYTES_PER_3AXIS_SENSOR 6
> #define INV_MPU6050_FIFO_COUNT_BYTE 2
> -#define INV_MPU6050_FIFO_THRESHOLD 500
>
> /* mpu6500 registers */
> #define INV_MPU6500_REG_ACCEL_CONFIG_2 0x1D
> diff --git a/drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c b/drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c
> index 7724888a4696..7a4aaed83044 100644
> --- a/drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c
> +++ b/drivers/iio/imu/inv_mpu6050/inv_mpu_ring.c
> @@ -110,6 +110,9 @@ irqreturn_t inv_mpu6050_read_fifo(int irq, void *p)
> "failed to ack interrupt\n");
> goto flush_fifo;
> }
> + /* handle fifo overflow by reseting fifo */
> + if (int_status & INV_MPU6050_BIT_FIFO_OVERFLOW_INT)
> + goto flush_fifo;
> if (!(int_status & INV_MPU6050_BIT_RAW_DATA_RDY_INT)) {
> dev_warn(regmap_get_device(st->map),
> "spurious interrupt with status 0x%x\n", int_status);
> @@ -135,8 +138,6 @@ irqreturn_t inv_mpu6050_read_fifo(int irq, void *p)
> if (result)
> goto end_session;
> fifo_count = get_unaligned_be16(&data[0]);
> - if (fifo_count > INV_MPU6050_FIFO_THRESHOLD)
> - goto flush_fifo;
> /* compute and process all complete datum */
> nb = fifo_count / bytes_per_datum;
> for (i = 0; i < nb; ++i) {
next prev parent reply other threads:[~2018-05-27 10:06 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-22 14:18 [PATCH v2 1/5] iio: imu: inv_mpu6050: replace timestamp fifo by generic timestamp Jean-Baptiste Maneyrol
2018-05-22 14:18 ` [PATCH v2 2/5] iio: imu: inv_mpu6050: switch to use sample rate divider Jean-Baptiste Maneyrol
2018-05-27 10:05 ` Jonathan Cameron
2018-05-22 14:18 ` [PATCH v2 3/5] iio: imu: inv_mpu6050: fix fifo count reading Jean-Baptiste Maneyrol
2018-05-27 10:06 ` Jonathan Cameron
2018-05-22 14:18 ` [PATCH v2 4/5] iio: imu: inv_mpu6050: better fifo overflow handling Jean-Baptiste Maneyrol
2018-05-27 10:06 ` Jonathan Cameron [this message]
2018-05-22 14:18 ` [PATCH v2 5/5] iio: imu: inv_mpu6050: new timestamp mechanism Jean-Baptiste Maneyrol
2018-05-27 10:07 ` Jonathan Cameron
2018-05-27 10:05 ` [PATCH v2 1/5] iio: imu: inv_mpu6050: replace timestamp fifo by generic timestamp Jonathan Cameron
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