diff for duplicates of <20180528002354.45025afd@xps13> diff --git a/a/1.txt b/N1/1.txt index 6496a3c..a7b4748 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -4,20 +4,18 @@ On Sun, 27 May 2018 23:54:38 +0200, Stefan Agner <stefan@agner.ch> wrote: > From: Lucas Stach <dev@lynxeye.de> ->=20 +> > This adds the devicetree binding for the Tegra 2 NAND flash > controller. ->=20 +> > Signed-off-by: Lucas Stach <dev@lynxeye.de> > Signed-off-by: Stefan Agner <stefan@agner.ch> > --- > .../bindings/mtd/nvidia,tegra20-nand.txt | 62 +++++++++++++++++++ > 1 file changed, 62 insertions(+) -> create mode 100644 Documentation/devicetree/bindings/mtd/nvidia,tegra20-= -nand.txt ->=20 -> diff --git a/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.tx= -t b/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt +> create mode 100644 Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt +> +> diff --git a/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt b/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt > new file mode 100644 > index 000000000000..49e472af1b39 > --- /dev/null @@ -49,17 +47,15 @@ Nitpick: just put the compatible here as there is only one? > +Required children node properties: > +- reg: An integer ranging from 1 to 6 representing the CS line to use. -=46rom 1? It usually starts at 0. +From 1? It usually starts at 0. > + > +Optional children node properties: -> +- nand-ecc-mode: String, operation mode of the NAND ecc mode. "hw" by de= -fault +> +- nand-ecc-mode: String, operation mode of the NAND ecc mode. "hw" by default > +- nand-ecc-algo: string, algorithm of NAND ECC. > + Supported values are: "rs", "bch". > +- nand-bus-width : 8 or 16 bus width if not present 8 -> +- nand-on-flash-bbt: boolean to enable on flash bbt option if not presen= -t false +> +- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false > +- nand-ecc-strength: integer representing the number of bits to correct > + per ECC step. Supported strength using HW ECC modes are: > + - RS: 4, 6, 8 @@ -77,34 +73,34 @@ instead. > + > + Example: > + nand@70008000 { -> + compatible =3D "nvidia,tegra20-nand"; -> + reg =3D <0x70008000 0x100>; -> + interrupts =3D <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; -> + clocks =3D <&tegra_car TEGRA20_CLK_NDFLASH>; -> + clock-names =3D "nand"; -> + resets =3D <&tegra_car 13>; -> + reset-names =3D "nand"; +> + compatible = "nvidia,tegra20-nand"; +> + reg = <0x70008000 0x100>; +> + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; +> + clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; +> + clock-names = "nand"; +> + resets = <&tegra_car 13>; +> + reset-names = "nand"; > + > + nand-chip@0 { -> + reg =3D <0>; -> + #address-cells =3D <1>; -> + #size-cells =3D <1>; -> + nand-bus-width =3D <8>; +> + reg = <0>; +> + #address-cells = <1>; +> + #size-cells = <1>; +> + nand-bus-width = <8>; > + nand-on-flash-bbt; -> + nand-ecc-algo =3D "bch"; -> + nand-ecc-step-size =3D <512>; +> + nand-ecc-algo = "bch"; +> + nand-ecc-step-size = <512>; In the driver you only refer to step sizes of 512 B, you can remove the property from the bindings. -> + nand-ecc-strength =3D <8>; -> + wp-gpios =3D <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; +> + nand-ecc-strength = <8>; +> + wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; > + }; > + }; ---=20 +-- Miquel Raynal, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering https://bootlin.com diff --git a/a/content_digest b/N1/content_digest index 8dbdc60..e7388da 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -35,20 +35,18 @@ "wrote:\n" "\n" "> From: Lucas Stach <dev@lynxeye.de>\n" - ">=20\n" + "> \n" "> This adds the devicetree binding for the Tegra 2 NAND flash\n" "> controller.\n" - ">=20\n" + "> \n" "> Signed-off-by: Lucas Stach <dev@lynxeye.de>\n" "> Signed-off-by: Stefan Agner <stefan@agner.ch>\n" "> ---\n" "> .../bindings/mtd/nvidia,tegra20-nand.txt | 62 +++++++++++++++++++\n" "> 1 file changed, 62 insertions(+)\n" - "> create mode 100644 Documentation/devicetree/bindings/mtd/nvidia,tegra20-=\n" - "nand.txt\n" - ">=20\n" - "> diff --git a/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.tx=\n" - "t b/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt\n" + "> create mode 100644 Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt\n" + "> \n" + "> diff --git a/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt b/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt\n" "> new file mode 100644\n" "> index 000000000000..49e472af1b39\n" "> --- /dev/null\n" @@ -80,17 +78,15 @@ "> +Required children node properties:\n" "> +- reg: An integer ranging from 1 to 6 representing the CS line to use.\n" "\n" - "=46rom 1? It usually starts at 0.\n" + "From 1? It usually starts at 0.\n" "\n" "> +\n" "> +Optional children node properties:\n" - "> +- nand-ecc-mode: String, operation mode of the NAND ecc mode. \"hw\" by de=\n" - "fault\n" + "> +- nand-ecc-mode: String, operation mode of the NAND ecc mode. \"hw\" by default\n" "> +- nand-ecc-algo: string, algorithm of NAND ECC.\n" "> +\t\t Supported values are: \"rs\", \"bch\".\n" "> +- nand-bus-width : 8 or 16 bus width if not present 8\n" - "> +- nand-on-flash-bbt: boolean to enable on flash bbt option if not presen=\n" - "t false\n" + "> +- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false\n" "> +- nand-ecc-strength: integer representing the number of bits to correct\n" "> +\t\t per ECC step. Supported strength using HW ECC modes are:\n" "> +\t\t - RS: 4, 6, 8\n" @@ -108,36 +104,36 @@ "> +\n" "> + Example:\n" "> +\tnand@70008000 {\n" - "> +\t\tcompatible =3D \"nvidia,tegra20-nand\";\n" - "> +\t\treg =3D <0x70008000 0x100>;\n" - "> +\t\tinterrupts =3D <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;\n" - "> +\t\tclocks =3D <&tegra_car TEGRA20_CLK_NDFLASH>;\n" - "> +\t\tclock-names =3D \"nand\";\n" - "> +\t\tresets =3D <&tegra_car 13>;\n" - "> +\t\treset-names =3D \"nand\";\n" + "> +\t\tcompatible = \"nvidia,tegra20-nand\";\n" + "> +\t\treg = <0x70008000 0x100>;\n" + "> +\t\tinterrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;\n" + "> +\t\tclocks = <&tegra_car TEGRA20_CLK_NDFLASH>;\n" + "> +\t\tclock-names = \"nand\";\n" + "> +\t\tresets = <&tegra_car 13>;\n" + "> +\t\treset-names = \"nand\";\n" "> +\n" "> +\t\tnand-chip@0 {\n" - "> +\t\t\treg =3D <0>;\n" - "> +\t\t\t#address-cells =3D <1>;\n" - "> +\t\t\t#size-cells =3D <1>;\n" - "> +\t\t\tnand-bus-width =3D <8>;\n" + "> +\t\t\treg = <0>;\n" + "> +\t\t\t#address-cells = <1>;\n" + "> +\t\t\t#size-cells = <1>;\n" + "> +\t\t\tnand-bus-width = <8>;\n" "> +\t\t\tnand-on-flash-bbt;\n" - "> +\t\t\tnand-ecc-algo =3D \"bch\";\n" - "> +\t\t\tnand-ecc-step-size =3D <512>;\n" + "> +\t\t\tnand-ecc-algo = \"bch\";\n" + "> +\t\t\tnand-ecc-step-size = <512>;\n" "\n" "In the driver you only refer to step sizes of 512 B, you can remove the\n" "property from the bindings.\n" "\n" - "> +\t\t\tnand-ecc-strength =3D <8>;\n" - "> +\t\t\twp-gpios =3D <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;\n" + "> +\t\t\tnand-ecc-strength = <8>;\n" + "> +\t\t\twp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;\n" "> +\t\t};\n" "> +\t};\n" "\n" "\n" "\n" - "--=20\n" + "-- \n" "Miquel Raynal, Bootlin (formerly Free Electrons)\n" "Embedded Linux and Kernel engineering\n" https://bootlin.com -58e1b764b9e131f306d88343af76b1aafe1911e901ee6eac5464a02ac63802d3 +32578ceec86a2eab39bf451675d5b5dae2c03a7b1d7633d47f806689c7a01c46
diff --git a/a/1.txt b/N2/1.txt index 6496a3c..6f349c0 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -4,20 +4,18 @@ On Sun, 27 May 2018 23:54:38 +0200, Stefan Agner <stefan@agner.ch> wrote: > From: Lucas Stach <dev@lynxeye.de> ->=20 +> > This adds the devicetree binding for the Tegra 2 NAND flash > controller. ->=20 +> > Signed-off-by: Lucas Stach <dev@lynxeye.de> > Signed-off-by: Stefan Agner <stefan@agner.ch> > --- > .../bindings/mtd/nvidia,tegra20-nand.txt | 62 +++++++++++++++++++ > 1 file changed, 62 insertions(+) -> create mode 100644 Documentation/devicetree/bindings/mtd/nvidia,tegra20-= -nand.txt ->=20 -> diff --git a/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.tx= -t b/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt +> create mode 100644 Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt +> +> diff --git a/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt b/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt > new file mode 100644 > index 000000000000..49e472af1b39 > --- /dev/null @@ -49,17 +47,15 @@ Nitpick: just put the compatible here as there is only one? > +Required children node properties: > +- reg: An integer ranging from 1 to 6 representing the CS line to use. -=46rom 1? It usually starts at 0. +>From 1? It usually starts at 0. > + > +Optional children node properties: -> +- nand-ecc-mode: String, operation mode of the NAND ecc mode. "hw" by de= -fault +> +- nand-ecc-mode: String, operation mode of the NAND ecc mode. "hw" by default > +- nand-ecc-algo: string, algorithm of NAND ECC. > + Supported values are: "rs", "bch". > +- nand-bus-width : 8 or 16 bus width if not present 8 -> +- nand-on-flash-bbt: boolean to enable on flash bbt option if not presen= -t false +> +- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false > +- nand-ecc-strength: integer representing the number of bits to correct > + per ECC step. Supported strength using HW ECC modes are: > + - RS: 4, 6, 8 @@ -77,34 +73,34 @@ instead. > + > + Example: > + nand@70008000 { -> + compatible =3D "nvidia,tegra20-nand"; -> + reg =3D <0x70008000 0x100>; -> + interrupts =3D <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; -> + clocks =3D <&tegra_car TEGRA20_CLK_NDFLASH>; -> + clock-names =3D "nand"; -> + resets =3D <&tegra_car 13>; -> + reset-names =3D "nand"; +> + compatible = "nvidia,tegra20-nand"; +> + reg = <0x70008000 0x100>; +> + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; +> + clocks = <&tegra_car TEGRA20_CLK_NDFLASH>; +> + clock-names = "nand"; +> + resets = <&tegra_car 13>; +> + reset-names = "nand"; > + > + nand-chip@0 { -> + reg =3D <0>; -> + #address-cells =3D <1>; -> + #size-cells =3D <1>; -> + nand-bus-width =3D <8>; +> + reg = <0>; +> + #address-cells = <1>; +> + #size-cells = <1>; +> + nand-bus-width = <8>; > + nand-on-flash-bbt; -> + nand-ecc-algo =3D "bch"; -> + nand-ecc-step-size =3D <512>; +> + nand-ecc-algo = "bch"; +> + nand-ecc-step-size = <512>; In the driver you only refer to step sizes of 512 B, you can remove the property from the bindings. -> + nand-ecc-strength =3D <8>; -> + wp-gpios =3D <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; +> + nand-ecc-strength = <8>; +> + wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>; > + }; > + }; ---=20 +-- Miquel Raynal, Bootlin (formerly Free Electrons) Embedded Linux and Kernel engineering https://bootlin.com diff --git a/a/content_digest b/N2/content_digest index 8dbdc60..72892c5 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -35,20 +35,18 @@ "wrote:\n" "\n" "> From: Lucas Stach <dev@lynxeye.de>\n" - ">=20\n" + "> \n" "> This adds the devicetree binding for the Tegra 2 NAND flash\n" "> controller.\n" - ">=20\n" + "> \n" "> Signed-off-by: Lucas Stach <dev@lynxeye.de>\n" "> Signed-off-by: Stefan Agner <stefan@agner.ch>\n" "> ---\n" "> .../bindings/mtd/nvidia,tegra20-nand.txt | 62 +++++++++++++++++++\n" "> 1 file changed, 62 insertions(+)\n" - "> create mode 100644 Documentation/devicetree/bindings/mtd/nvidia,tegra20-=\n" - "nand.txt\n" - ">=20\n" - "> diff --git a/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.tx=\n" - "t b/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt\n" + "> create mode 100644 Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt\n" + "> \n" + "> diff --git a/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt b/Documentation/devicetree/bindings/mtd/nvidia,tegra20-nand.txt\n" "> new file mode 100644\n" "> index 000000000000..49e472af1b39\n" "> --- /dev/null\n" @@ -80,17 +78,15 @@ "> +Required children node properties:\n" "> +- reg: An integer ranging from 1 to 6 representing the CS line to use.\n" "\n" - "=46rom 1? It usually starts at 0.\n" + ">From 1? It usually starts at 0.\n" "\n" "> +\n" "> +Optional children node properties:\n" - "> +- nand-ecc-mode: String, operation mode of the NAND ecc mode. \"hw\" by de=\n" - "fault\n" + "> +- nand-ecc-mode: String, operation mode of the NAND ecc mode. \"hw\" by default\n" "> +- nand-ecc-algo: string, algorithm of NAND ECC.\n" "> +\t\t Supported values are: \"rs\", \"bch\".\n" "> +- nand-bus-width : 8 or 16 bus width if not present 8\n" - "> +- nand-on-flash-bbt: boolean to enable on flash bbt option if not presen=\n" - "t false\n" + "> +- nand-on-flash-bbt: boolean to enable on flash bbt option if not present false\n" "> +- nand-ecc-strength: integer representing the number of bits to correct\n" "> +\t\t per ECC step. Supported strength using HW ECC modes are:\n" "> +\t\t - RS: 4, 6, 8\n" @@ -108,36 +104,36 @@ "> +\n" "> + Example:\n" "> +\tnand@70008000 {\n" - "> +\t\tcompatible =3D \"nvidia,tegra20-nand\";\n" - "> +\t\treg =3D <0x70008000 0x100>;\n" - "> +\t\tinterrupts =3D <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;\n" - "> +\t\tclocks =3D <&tegra_car TEGRA20_CLK_NDFLASH>;\n" - "> +\t\tclock-names =3D \"nand\";\n" - "> +\t\tresets =3D <&tegra_car 13>;\n" - "> +\t\treset-names =3D \"nand\";\n" + "> +\t\tcompatible = \"nvidia,tegra20-nand\";\n" + "> +\t\treg = <0x70008000 0x100>;\n" + "> +\t\tinterrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;\n" + "> +\t\tclocks = <&tegra_car TEGRA20_CLK_NDFLASH>;\n" + "> +\t\tclock-names = \"nand\";\n" + "> +\t\tresets = <&tegra_car 13>;\n" + "> +\t\treset-names = \"nand\";\n" "> +\n" "> +\t\tnand-chip@0 {\n" - "> +\t\t\treg =3D <0>;\n" - "> +\t\t\t#address-cells =3D <1>;\n" - "> +\t\t\t#size-cells =3D <1>;\n" - "> +\t\t\tnand-bus-width =3D <8>;\n" + "> +\t\t\treg = <0>;\n" + "> +\t\t\t#address-cells = <1>;\n" + "> +\t\t\t#size-cells = <1>;\n" + "> +\t\t\tnand-bus-width = <8>;\n" "> +\t\t\tnand-on-flash-bbt;\n" - "> +\t\t\tnand-ecc-algo =3D \"bch\";\n" - "> +\t\t\tnand-ecc-step-size =3D <512>;\n" + "> +\t\t\tnand-ecc-algo = \"bch\";\n" + "> +\t\t\tnand-ecc-step-size = <512>;\n" "\n" "In the driver you only refer to step sizes of 512 B, you can remove the\n" "property from the bindings.\n" "\n" - "> +\t\t\tnand-ecc-strength =3D <8>;\n" - "> +\t\t\twp-gpios =3D <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;\n" + "> +\t\t\tnand-ecc-strength = <8>;\n" + "> +\t\t\twp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;\n" "> +\t\t};\n" "> +\t};\n" "\n" "\n" "\n" - "--=20\n" + "-- \n" "Miquel Raynal, Bootlin (formerly Free Electrons)\n" "Embedded Linux and Kernel engineering\n" https://bootlin.com -58e1b764b9e131f306d88343af76b1aafe1911e901ee6eac5464a02ac63802d3 +d77527e488a4b634aa11fffa5e060699a85bed5cd06dfe24a7627c6957f12b7e
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