From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail.bootlin.com ([62.4.15.54]) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1fQrhH-0002bN-PA for linux-mtd@lists.infradead.org; Thu, 07 Jun 2018 09:59:13 +0000 Date: Thu, 7 Jun 2018 11:58:48 +0200 From: Miquel Raynal To: Stefan Agner Cc: boris.brezillon@bootlin.com, dwmw2@infradead.org, computersforpeace@gmail.com, marek.vasut@gmail.com, robh+dt@kernel.org, mark.rutland@arm.com, thierry.reding@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, dev@lynxeye.de, richard@nod.at, marcel@ziswiler.com, krzk@kernel.org, digetx@gmail.com, benjamin.lindqvist@endian.se, jonathanh@nvidia.com, pdeschrijver@nvidia.com, pgaikwad@nvidia.com, mirza.krak@gmail.com, linux-mtd@lists.infradead.org, linux-tegra@vger.kernel.org Subject: Re: [PATCH v2 3/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver Message-ID: <20180607115848.5ef08680@xps13> In-Reply-To: <80eb6a514e96cdbd460c6a0937a9dff9@agner.ch> References: <20180527215442.14760-4-stefan@agner.ch> <80eb6a514e96cdbd460c6a0937a9dff9@agner.ch> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable List-Id: Linux MTD discussion mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Hi Stefan, On Thu, 31 May 2018 11:37:41 +0200, Stefan Agner wrote: > On 27.05.2018 23:54, Stefan Agner wrote: > > Add support for the NAND flash controller found on NVIDIA > > Tegra 2 SoCs. This implementation does not make use of the > > command queue feature. Regular operations/data transfers are > > done in PIO mode. Page read/writes with hardware ECC make > > use of the DMA for data transfer. > >=20 > > Signed-off-by: Lucas Stach > > Signed-off-by: Stefan Agner > > --- > > MAINTAINERS | 7 + > > drivers/mtd/nand/raw/Kconfig | 6 + > > drivers/mtd/nand/raw/Makefile | 1 + > > drivers/mtd/nand/raw/tegra_nand.c | 999 ++++++++++++++++++++++++++++++ > > 4 files changed, 1013 insertions(+) > > create mode 100644 drivers/mtd/nand/raw/tegra_nand.c > > =20 > [...] > > + > > + chip->ecc.read_page =3D tegra_nand_read_page_hwecc; > > + chip->ecc.write_page =3D tegra_nand_write_page_hwecc; > > + /* Not functional for unknown reason... > > + chip->ecc.read_page_raw =3D tegra_nand_read_page; > > + chip->ecc.write_page_raw =3D tegra_nand_write_page; > > + */ =20 >=20 > I am giving up on these raw read/write_page functions. Using DMA without > HW ECC just seems not to work. [...] > Note that the default implementations nand_(read|write)_page_raw which > use exec_op do work fine! Unfortunately, the PIO mode only allows 4 > bytes in a read cycle, hence raw read/write is slow... >=20 Well, if raw accessors work in PIO mode, I suppose it's not a big deal. Thanks for trying anyway! Miqu=C3=A8l From mboxrd@z Thu Jan 1 00:00:00 1970 From: Miquel Raynal Subject: Re: [PATCH v2 3/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver Date: Thu, 7 Jun 2018 11:58:48 +0200 Message-ID: <20180607115848.5ef08680@xps13> References: <20180527215442.14760-4-stefan@agner.ch> <80eb6a514e96cdbd460c6a0937a9dff9@agner.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <80eb6a514e96cdbd460c6a0937a9dff9@agner.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-mtd" Errors-To: linux-mtd-bounces+gldm-linux-mtd-36=gmane.org@lists.infradead.org To: Stefan Agner Cc: mark.rutland@arm.com, pgaikwad@nvidia.com, dev@lynxeye.de, marek.vasut@gmail.com, sboyd@kernel.org, richard@nod.at, mturquette@baylibre.com, mirza.krak@gmail.com, krzk@kernel.org, jonathanh@nvidia.com, boris.brezillon@bootlin.com, robh+dt@kernel.org, thierry.reding@gmail.com, marcel@ziswiler.com, benjamin.lindqvist@endian.se, linux-tegra@vger.kernel.org, linux-mtd@lists.infradead.org, digetx@gmail.com, computersforpeace@gmail.com, dwmw2@infradead.org, pdeschrijver@nvidia.com List-Id: linux-tegra@vger.kernel.org SGkgU3RlZmFuLAoKT24gVGh1LCAzMSBNYXkgMjAxOCAxMTozNzo0MSArMDIwMCwgU3RlZmFuIEFn bmVyIDxzdGVmYW5AYWduZXIuY2g+Cndyb3RlOgoKPiBPbiAyNy4wNS4yMDE4IDIzOjU0LCBTdGVm YW4gQWduZXIgd3JvdGU6Cj4gPiBBZGQgc3VwcG9ydCBmb3IgdGhlIE5BTkQgZmxhc2ggY29udHJv bGxlciBmb3VuZCBvbiBOVklESUEKPiA+IFRlZ3JhIDIgU29Dcy4gVGhpcyBpbXBsZW1lbnRhdGlv biBkb2VzIG5vdCBtYWtlIHVzZSBvZiB0aGUKPiA+IGNvbW1hbmQgcXVldWUgZmVhdHVyZS4gUmVn dWxhciBvcGVyYXRpb25zL2RhdGEgdHJhbnNmZXJzIGFyZQo+ID4gZG9uZSBpbiBQSU8gbW9kZS4g UGFnZSByZWFkL3dyaXRlcyB3aXRoIGhhcmR3YXJlIEVDQyBtYWtlCj4gPiB1c2Ugb2YgdGhlIERN QSBmb3IgZGF0YSB0cmFuc2Zlci4KPiA+IAo+ID4gU2lnbmVkLW9mZi1ieTogTHVjYXMgU3RhY2gg PGRldkBseW54ZXllLmRlPgo+ID4gU2lnbmVkLW9mZi1ieTogU3RlZmFuIEFnbmVyIDxzdGVmYW5A YWduZXIuY2g+Cj4gPiAtLS0KPiA+ICBNQUlOVEFJTkVSUyAgICAgICAgICAgICAgICAgICAgICAg fCAgIDcgKwo+ID4gIGRyaXZlcnMvbXRkL25hbmQvcmF3L0tjb25maWcgICAgICB8ICAgNiArCj4g PiAgZHJpdmVycy9tdGQvbmFuZC9yYXcvTWFrZWZpbGUgICAgIHwgICAxICsKPiA+ICBkcml2ZXJz L210ZC9uYW5kL3Jhdy90ZWdyYV9uYW5kLmMgfCA5OTkgKysrKysrKysrKysrKysrKysrKysrKysr KysrKysrCj4gPiAgNCBmaWxlcyBjaGFuZ2VkLCAxMDEzIGluc2VydGlvbnMoKykKPiA+ICBjcmVh dGUgbW9kZSAxMDA2NDQgZHJpdmVycy9tdGQvbmFuZC9yYXcvdGVncmFfbmFuZC5jCj4gPiAgIAo+ IFsuLi5dCj4gPiArCj4gPiArCWNoaXAtPmVjYy5yZWFkX3BhZ2UgPSB0ZWdyYV9uYW5kX3JlYWRf cGFnZV9od2VjYzsKPiA+ICsJY2hpcC0+ZWNjLndyaXRlX3BhZ2UgPSB0ZWdyYV9uYW5kX3dyaXRl X3BhZ2VfaHdlY2M7Cj4gPiArCS8qIE5vdCBmdW5jdGlvbmFsIGZvciB1bmtub3duIHJlYXNvbi4u Lgo+ID4gKwljaGlwLT5lY2MucmVhZF9wYWdlX3JhdyA9IHRlZ3JhX25hbmRfcmVhZF9wYWdlOwo+ ID4gKwljaGlwLT5lY2Mud3JpdGVfcGFnZV9yYXcgPSB0ZWdyYV9uYW5kX3dyaXRlX3BhZ2U7Cj4g PiArCSovICAKPiAKPiBJIGFtIGdpdmluZyB1cCBvbiB0aGVzZSByYXcgcmVhZC93cml0ZV9wYWdl IGZ1bmN0aW9ucy4gVXNpbmcgRE1BIHdpdGhvdXQKPiBIVyBFQ0MganVzdCBzZWVtcyBub3QgdG8g d29yay4KClsuLi5dCgo+IE5vdGUgdGhhdCB0aGUgZGVmYXVsdCBpbXBsZW1lbnRhdGlvbnMgbmFu ZF8ocmVhZHx3cml0ZSlfcGFnZV9yYXcgd2hpY2gKPiB1c2UgZXhlY19vcCBkbyB3b3JrIGZpbmUh IFVuZm9ydHVuYXRlbHksIHRoZSBQSU8gbW9kZSBvbmx5IGFsbG93cyA0Cj4gYnl0ZXMgaW4gYSBy ZWFkIGN5Y2xlLCBoZW5jZSByYXcgcmVhZC93cml0ZSBpcyBzbG93Li4uCj4gCgpXZWxsLCBpZiBy YXcgYWNjZXNzb3JzIHdvcmsgaW4gUElPIG1vZGUsIEkgc3VwcG9zZSBpdCdzIG5vdCBhIGJpZyBk ZWFsLgoKVGhhbmtzIGZvciB0cnlpbmcgYW55d2F5IQpNaXF1w6hsCgpfX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KTGludXggTVREIGRpc2N1c3Np b24gbWFpbGluZyBsaXN0Cmh0dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGlu Zm8vbGludXgtbXRkLwo=