From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (146.0.238.70:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 12 Jun 2018 20:51:16 -0000 Received: from aserp2120.oracle.com ([141.146.126.78]) by Galois.linutronix.de with esmtps (TLS1.2:RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1fSqG3-0004KZ-BE for speck@linutronix.de; Tue, 12 Jun 2018 22:51:16 +0200 Received: from pps.filterd (aserp2120.oracle.com [127.0.0.1]) by aserp2120.oracle.com (8.16.0.22/8.16.0.22) with SMTP id w5CKkIRK072937 for ; Tue, 12 Jun 2018 20:51:08 GMT Received: from aserv0021.oracle.com (aserv0021.oracle.com [141.146.126.233]) by aserp2120.oracle.com with ESMTP id 2jgecxk1a5-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Tue, 12 Jun 2018 20:51:08 +0000 Received: from aserv0122.oracle.com (aserv0122.oracle.com [141.146.126.236]) by aserv0021.oracle.com (8.14.4/8.14.4) with ESMTP id w5CKp8Nh020775 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Tue, 12 Jun 2018 20:51:08 GMT Received: from abhmp0006.oracle.com (abhmp0006.oracle.com [141.146.116.12]) by aserv0122.oracle.com (8.14.4/8.14.4) with ESMTP id w5CKp7No024580 for ; Tue, 12 Jun 2018 20:51:08 GMT Date: Tue, 12 Jun 2018 16:51:06 -0400 From: Konrad Rzeszutek Wilk Subject: [MODERATED] Re: [patch V2 12/12] x86/apic: Ignore secondary threads if nosmt=force Message-ID: <20180612205106.GK25607@char.us.oracle.com> References: <20180606192714.754943543@linutronix.de> <20180606192807.929619226@linutronix.de> MIME-Version: 1.0 In-Reply-To: <20180606192807.929619226@linutronix.de> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Wed, Jun 06, 2018 at 09:27:26PM +0200, speck for Thomas Gleixner wrote: > Subject: [patch V2 12/12] x86/apic: Ignore secondary threads if nosmt=force > From: Thomas Gleixner > > nosmt on the kernel command line merily prevents the onlining of the > secondary SMT siblings. > > nosmt=force makes the APIC detection code ignore the secondary SMT siblings > completely, so they even do not show up as possible CPUs. This is more or > less equivalent to disabling SMT in the BIOS. > > Signed-off-by: Thomas Gleixner > --- > arch/x86/include/asm/apic.h | 2 ++ > arch/x86/kernel/acpi/boot.c | 3 ++- > arch/x86/kernel/apic/apic.c | 21 ++++++++++++++++++++- > 3 files changed, 24 insertions(+), 2 deletions(-) > > --- a/arch/x86/include/asm/apic.h > +++ b/arch/x86/include/asm/apic.h > @@ -502,8 +502,10 @@ extern int default_check_phys_apicid_pre > > #ifdef CONFIG_SMP > bool apic_id_is_primary_thread(unsigned int id); > +bool apic_id_disabled(unsigned int id); > #else > static inline bool apic_id_is_primary_thread(unsigned int id) { return false; } > +static inline bool apic_id_disabled(unsigned int id) { return false; } > #endif > > extern void irq_enter(void); > --- a/arch/x86/kernel/acpi/boot.c > +++ b/arch/x86/kernel/acpi/boot.c > @@ -181,7 +181,8 @@ static int acpi_register_lapic(int id, u > } > > if (!enabled) { > - ++disabled_cpus; > + if (!apic_id_disabled(id)) > + ++disabled_cpus; > return -EINVAL; > } > > --- a/arch/x86/kernel/apic/apic.c > +++ b/arch/x86/kernel/apic/apic.c > @@ -2200,10 +2200,20 @@ bool apic_id_is_primary_thread(unsigned > if (smp_num_siblings == 1) > return true; > /* Isolate the SMT bit(s) in the APICID and check for 0 */ > - mask = (1U << fls(smp_num_siblings) - 1) - 1; > + mask = (1U << (fls(smp_num_siblings) - 1)) - 1; Should this be squashed in patch "8a9d907a102d x86/smp: Provide topology_is_primary_thread()" ? > return !(apicid & mask); > } > > +/** > + * apic_id_disabled - Check whether APIC ID is disabled via SMT control > + * @id: APIC ID to check > + */ > +bool apic_id_disabled(unsigned int id) > +{ > + return (cpu_smt_control == CPU_SMT_FORCE_DISABLED && > + !apic_id_is_primary_thread(id)); > +} > + > /* > * Should use this API to allocate logical CPU IDs to keep nr_logical_cpuids > * and cpuid_to_apicid[] synchronized. > @@ -2299,6 +2309,15 @@ int generic_processor_info(int apicid, i > return -EINVAL; > } > > + /* > + * If SMT is force disabled and the APIC ID belongs to > + * a secondary thread, ignore it. > + */ > + if (apic_id_disabled(apicid)) { > + pr_info_once("Ignoring secondary SMT threads\n"); > + return -EINVAL; > + } > + Ouch. Besides the above comment (squash): Reviewed-by: Konrad Rzeszutek Wilk > if (apicid == boot_cpu_physical_apicid) { > /* > * x86_bios_cpu_apicid is required to have processors listed >