From: Shreyas NC <shreyas.nc@intel.com>
To: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Cc: patches.audio@intel.com, gregkh@linuxfoundation.org,
Sanyog Kale <sanyog.r.kale@intel.com>,
alsa-devel@alsa-project.org, vkoul@kernel.org
Subject: Re: [PATCH v2 4/6] soundwire: Handle multiple master instances in a stream
Date: Thu, 14 Jun 2018 08:42:43 +0530 [thread overview]
Message-ID: <20180614031242.GN3116@snc-desk> (raw)
In-Reply-To: <e34a35a8-9c2d-b254-65d2-012d57d5f528@linux.intel.com>
> >>>+
> >>>+ /* Bank switch */
> >>>+ ret = sdw_bank_switch(bus);
> >>> if (ret < 0) {
> >>>- dev_err(bus->dev, "Pre bank switch op failed: %d", ret);
> >>>+ dev_err(bus->dev, "Bank switch failed: %d", ret);
> >>> return ret;
> >>> }
> >>You probably want to add a comment that in multi-link operation the actual
> >>bank_switch happens later and is done in a synchronized manner. This is lost
> >>if you just move code around and move the bank_switch into a loop.
> >>
> >>I am actually no longer clear just looking at this code on when the
> >>bank_switch happens (i know we've discussed this before but I am trying to
> >>find out just based on this v2 instead of projecting how I think it should
> >>work):
> >>In Patch 6/6 it's pretty obvious that the bank switch happens when the
> >>SyncGO bit is set, but there is no comment or explanation on how we reach
> >>the intel_post_bank_switch() routine once for all masters handling a stream
> >>when everything is based on loops. Clearly the intel_pre_bank_switch is
> >>called multiple times (once per master), I guess I am missing what the
> >>trigger is for the intel_post_bank_switch() routine to be invoked?
> >>
> >
> >Hi Pierre,
> >
> >To answer your last question, do_bank_switch is where we perform all the
> >bank switch operations.
> >
> >In first loop for Master(s) involved in stream, ops->pre_bank_switch and
> >bank_switch is performed. In 2nd loop for Master(s) involved in stream,
> >ops->post_bank_switch and wait for bank switch is performed.
> >
> >Assuming a stream with Master 1 and Master 2, the go_sync bit will be
> >set in Master 1 intel_post_bank_switch call which will trigger bank
> >switch for both the Master's. The Master 2 intel_post_bank_switch call
> >will just return as it will won't see CMDSYNC bit set for any Master(s).
>
> Makes sense, thanks for taking the time to provide the details I didn't
> remember.
> Sreyas, if you could add a bit of information on this it'd be a good thing -
> specifically the expectation is that the bank switch is triggered by the
> first master in the master_list loop while others just return without doing
> anything.
>
Sure, makes sense. I will add these details in the relevant patch.
--Shreyas
--
next prev parent reply other threads:[~2018-06-14 3:14 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-12 10:53 [PATCH v2 0/6] soundwire: Add multi link support Shreyas NC
2018-06-12 10:53 ` [PATCH v2 1/6] Documentation: soundwire: Add documentation for Multi link Shreyas NC
2018-06-12 10:53 ` [PATCH v2 2/6] soundwire: Initialize completion for defer messages Shreyas NC
2018-06-12 10:53 ` [PATCH v2 3/6] soundwire: Add support to lock across bus instances Shreyas NC
2018-06-12 10:53 ` [PATCH v2 4/6] soundwire: Handle multiple master instances in a stream Shreyas NC
2018-06-12 19:12 ` Pierre-Louis Bossart
2018-06-13 5:54 ` Sanyog Kale
2018-06-13 16:55 ` Pierre-Louis Bossart
2018-06-14 3:12 ` Shreyas NC [this message]
2018-06-13 10:45 ` Shreyas NC
2018-06-12 10:53 ` [PATCH v2 5/6] soundwire: Add support for multilink bank switch Shreyas NC
2018-06-12 10:53 ` [PATCH v2 6/6] soundwire: intel: Add pre/post bank switch ops Shreyas NC
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