From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: "José Roberto de Souza" <jose.souza@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Subject: Re: [PATCH v4 4/5] drm/i915/psr: Avoid PSR exit max time timeout
Date: Thu, 14 Jun 2018 14:13:12 -0700 [thread overview]
Message-ID: <20180614211312.GX8374@intel.com> (raw)
In-Reply-To: <20180614203433.5602-4-jose.souza@intel.com>
On Thu, Jun 14, 2018 at 01:34:32PM -0700, José Roberto de Souza wrote:
> Specification requires that max time should be masked from bdw and
> forward but it can be also safely enabled to hsw.
> This will make PSR exits more deterministic and only when really
> needed. If this was used to fix a issue in some panel than can
> only self-refresh for a few seconds, that panel will interrupt
> and assert one of the PSR errors handled in:
> 'drm/i915/psr: Handle PSR RFB storage error' and
> 'drm/i915/psr: Begin to handle PSR/PSR2 errors set by sink'
>
> Also fixing style here.
I don't believe that is a style error. So I believe only
the MAX_SLEEP one should be added following same style.
>
> Spec: 21664
>
> v4:
> patch moved to before 'drm/i915/psr/bdw+: Enable CRC check in the
> static frame on the sink side' to avoid touch in 2 patches
> EDP_PSR_DEBUG.
I thought this change here depended on having CRC check enabled
so it should come first and only bdw+...
Isn't this the case?
>
> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/intel_psr.c | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index fd240e45f341..177cd57b1029 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -629,10 +629,11 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp,
> * on frontbuffer tracking.
> */
> I915_WRITE(EDP_PSR_DEBUG,
> - EDP_PSR_DEBUG_MASK_MEMUP |
> - EDP_PSR_DEBUG_MASK_HPD |
> - EDP_PSR_DEBUG_MASK_LPSP |
> - EDP_PSR_DEBUG_MASK_DISP_REG_WRITE);
> + EDP_PSR_DEBUG_MASK_MEMUP |
> + EDP_PSR_DEBUG_MASK_HPD |
> + EDP_PSR_DEBUG_MASK_LPSP |
> + EDP_PSR_DEBUG_MASK_DISP_REG_WRITE |
> + EDP_PSR_DEBUG_MASK_MAX_SLEEP);
> }
> }
>
> --
> 2.17.1
>
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next prev parent reply other threads:[~2018-06-14 21:13 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-14 20:34 [PATCH v4 1/5] drm/i915/psr: Remove intel_crtc_state parameter from disable() José Roberto de Souza
2018-06-14 20:34 ` [PATCH v4 2/5] drm/i915/psr: Begin to handle PSR/PSR2 errors set by sink José Roberto de Souza
2018-06-14 21:09 ` Rodrigo Vivi
2018-06-14 21:59 ` Dhinakaran Pandiyan
2018-06-14 23:46 ` Souza, Jose
2018-06-14 23:59 ` Rodrigo Vivi
2018-06-15 0:11 ` Souza, Jose
2018-06-15 5:16 ` Rodrigo Vivi
2018-06-14 20:34 ` [PATCH v4 3/5] drm/i915/psr: Handle PSR RFB storage error José Roberto de Souza
2018-06-14 20:34 ` [PATCH v4 4/5] drm/i915/psr: Avoid PSR exit max time timeout José Roberto de Souza
2018-06-14 21:13 ` Rodrigo Vivi [this message]
2018-06-14 21:50 ` Dhinakaran Pandiyan
2018-06-14 21:50 ` Rodrigo Vivi
2018-06-14 22:02 ` Dhinakaran Pandiyan
2018-06-14 20:34 ` [PATCH v4 5/5] drm/i915/psr/bdw+: Enable CRC check in the static frame on the sink side José Roberto de Souza
2018-06-14 21:19 ` Rodrigo Vivi
2018-06-14 21:54 ` Dhinakaran Pandiyan
2018-06-15 0:02 ` Souza, Jose
2018-06-15 5:14 ` Rodrigo Vivi
2018-06-14 20:42 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [v4,1/5] drm/i915/psr: Remove intel_crtc_state parameter from disable() Patchwork
2018-06-14 20:44 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-06-14 20:57 ` ✓ Fi.CI.BAT: success " Patchwork
2018-06-15 5:49 ` ✓ Fi.CI.IGT: " Patchwork
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