From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Chris Packham <chris.packham@alliedtelesis.co.nz>
Cc: boris.brezillon@bootlin.com, dwmw2@infradead.org,
computersforpeace@gmail.com, linux-mtd@lists.infradead.org,
linux-kernel@vger.kernel.org, Richard Weinberger <richard@nod.at>,
Marek Vasut <marek.vasut@gmail.com>
Subject: Re: [RFC PATCH 2/2] mtd: rawnand: marvell: Support page size of 2048 with 8-bit ECC
Date: Mon, 18 Jun 2018 15:37:03 +0200 [thread overview]
Message-ID: <20180618153703.77bc01c1@xps13> (raw)
In-Reply-To: <20180618045255.8015-3-chris.packham@alliedtelesis.co.nz>
Hi Chris,
On Mon, 18 Jun 2018 16:52:55 +1200, Chris Packham
<chris.packham@alliedtelesis.co.nz> wrote:
> The MT29F1G08ABAFAWP-ITE:F chip has 2048 byte pages and requires a
> minimum ECC strength of 8-bits. Allow for this combination of
> requirements using the marvell_nand controller.
>
> Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
> ---
> I've tried to follow the recommended AN-379 from Marvell. They do seem
> to have information that covers this particular set of chip requirements
> but I'm not confident I've translated their code correctly into the
> current marvell_nand implementation.
>
> This is enough to make the nand_scan work but ubi/ubifs fails to initialise
> and/or mount so I may have something completely wrong. This may also be
> because this chip has internal ECC enabled which cannot be disabled. I
> turned up an old thread on this from April last year[1] but I didn't see
> anything resulting from this. Can this combination of ECC
> implementations even co-exist?
>
> [1] - http://lists.infradead.org/pipermail/linux-mtd/2017-April/073370.html
>
> drivers/mtd/nand/raw/marvell_nand.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/mtd/nand/raw/marvell_nand.c b/drivers/mtd/nand/raw/marvell_nand.c
> index ebb1d141b900..5712df553a8e 100644
> --- a/drivers/mtd/nand/raw/marvell_nand.c
> +++ b/drivers/mtd/nand/raw/marvell_nand.c
> @@ -217,6 +217,7 @@ static const struct marvell_hw_ecc_layout marvell_nfc_layouts[] = {
> MARVELL_LAYOUT( 512, 512, 1, 1, 1, 512, 8, 8, 0, 0, 0),
> MARVELL_LAYOUT( 2048, 512, 1, 1, 1, 2048, 40, 24, 0, 0, 0),
> MARVELL_LAYOUT( 2048, 512, 4, 1, 1, 2048, 32, 30, 0, 0, 0),
> + MARVELL_LAYOUT( 2048, 512, 8, 1, 1, 1024, 0, 30, 1024, 32, 30),
I suppose you should not use HW_ECC for this chip. Hence this line is
useless. However I think it should be:
MARVELL_LAYOUT( 2048, 512, 8, 2, 1, 1024, 0, 30, 1024, 32, 30),
^
> MARVELL_LAYOUT( 4096, 512, 4, 2, 2, 2048, 32, 30, 0, 0, 0),
> MARVELL_LAYOUT( 4096, 512, 8, 5, 4, 1024, 0, 30, 0, 64, 30),
> };
Regards,
Miquèl
next prev parent reply other threads:[~2018-06-18 13:37 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-18 4:52 [RFC PATCH 0/2] mtd: rawnand: support MT29F1G08ABAFAWP-ITE:F Chris Packham
2018-06-18 4:52 ` [RFC PATCH 1/2] mtd: rawnand: handle ONFI revision number field being 0 Chris Packham
2018-06-18 13:05 ` Miquel Raynal
2018-06-18 13:17 ` Boris Brezillon
2018-06-18 4:52 ` [RFC PATCH 2/2] mtd: rawnand: marvell: Support page size of 2048 with 8-bit ECC Chris Packham
2018-06-18 13:37 ` Miquel Raynal [this message]
2018-06-18 13:14 ` [RFC PATCH 0/2] mtd: rawnand: support MT29F1G08ABAFAWP-ITE:F Miquel Raynal
2018-06-19 0:35 ` Chris Packham
2018-06-19 1:44 ` Chris Packham
2018-06-19 4:55 ` Boris Brezillon
2018-06-19 23:56 ` Chris Packham
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