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diff for duplicates of <20180619170307.33232.70445@harbor.lan>

diff --git a/a/1.txt b/N1/1.txt
index 22dc33b..7727fb3 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -2,18 +2,15 @@ Quoting Jerome Brunet (2018-06-19 06:40:50)
 > the mmci driver (drivers/mmc/host/mmci.c) does the following sequence:
 > * clk_prepare_enable()
 > * clk_set_rate()
-> =
-
+> 
 > on SDCx_clk which is a children of SDCx_src. SDCx_src has
 > CLK_SET_RATE_GATE so this sequence should not be allowed but this was not
 > enforced. IOW, the flag is ignored. Dropping the flag won't change
 > anything to the current behaviour of the platform.
-> =
-
+> 
 > CLK_SET_RATE_GATE is being fixed and enforced now. If the flag was kept,
 > the mmci driver would receive -EBUSY when calling clk_set_rate()
-> =
-
+> 
 > Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
 
 Applied to clk-qcom-set-rate-gate.
@@ -27,149 +24,143 @@ Mike
 >  drivers/clk/qcom/gcc-msm8660.c | 5 -----
 >  drivers/clk/qcom/gcc-msm8960.c | 5 -----
 >  4 files changed, 15 deletions(-)
-> =
-
-> diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806=
-x.c
+> 
+> diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
 > index 28eb200d0f1e..5f61225657ab 100644
 > --- a/drivers/clk/qcom/gcc-ipq806x.c
 > +++ b/drivers/clk/qcom/gcc-ipq806x.c
-> @@ -1220,7 +1220,6 @@ static struct clk_rcg sdc1_src =3D {
->                         .parent_names =3D gcc_pxo_pll8,
->                         .num_parents =3D 2,
->                         .ops =3D &clk_rcg_ops,
-> -                       .flags =3D CLK_SET_RATE_GATE,
+> @@ -1220,7 +1220,6 @@ static struct clk_rcg sdc1_src = {
+>                         .parent_names = gcc_pxo_pll8,
+>                         .num_parents = 2,
+>                         .ops = &clk_rcg_ops,
+> -                       .flags = CLK_SET_RATE_GATE,
 >                 },
 >         }
 >  };
-> @@ -1269,7 +1268,6 @@ static struct clk_rcg sdc3_src =3D {
->                         .parent_names =3D gcc_pxo_pll8,
->                         .num_parents =3D 2,
->                         .ops =3D &clk_rcg_ops,
-> -                       .flags =3D CLK_SET_RATE_GATE,
+> @@ -1269,7 +1268,6 @@ static struct clk_rcg sdc3_src = {
+>                         .parent_names = gcc_pxo_pll8,
+>                         .num_parents = 2,
+>                         .ops = &clk_rcg_ops,
+> -                       .flags = CLK_SET_RATE_GATE,
 >                 },
 >         }
 >  };
-> @@ -1353,7 +1351,6 @@ static struct clk_rcg tsif_ref_src =3D {
->                         .parent_names =3D gcc_pxo_pll8,
->                         .num_parents =3D 2,
->                         .ops =3D &clk_rcg_ops,
-> -                       .flags =3D CLK_SET_RATE_GATE,
+> @@ -1353,7 +1351,6 @@ static struct clk_rcg tsif_ref_src = {
+>                         .parent_names = gcc_pxo_pll8,
+>                         .num_parents = 2,
+>                         .ops = &clk_rcg_ops,
+> -                       .flags = CLK_SET_RATE_GATE,
 >                 },
 >         }
 >  };
-> diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm961=
-5.c
+> diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c
 > index b99dd406e907..849046fbed6d 100644
 > --- a/drivers/clk/qcom/gcc-mdm9615.c
 > +++ b/drivers/clk/qcom/gcc-mdm9615.c
-> @@ -947,7 +947,6 @@ static struct clk_rcg sdc1_src =3D {
->                         .parent_names =3D gcc_cxo_pll8,
->                         .num_parents =3D 2,
->                         .ops =3D &clk_rcg_ops,
-> -                       .flags =3D CLK_SET_RATE_GATE,
+> @@ -947,7 +947,6 @@ static struct clk_rcg sdc1_src = {
+>                         .parent_names = gcc_cxo_pll8,
+>                         .num_parents = 2,
+>                         .ops = &clk_rcg_ops,
+> -                       .flags = CLK_SET_RATE_GATE,
 >                 },
 >         }
 >  };
-> @@ -996,7 +995,6 @@ static struct clk_rcg sdc2_src =3D {
->                         .parent_names =3D gcc_cxo_pll8,
->                         .num_parents =3D 2,
->                         .ops =3D &clk_rcg_ops,
-> -                       .flags =3D CLK_SET_RATE_GATE,
+> @@ -996,7 +995,6 @@ static struct clk_rcg sdc2_src = {
+>                         .parent_names = gcc_cxo_pll8,
+>                         .num_parents = 2,
+>                         .ops = &clk_rcg_ops,
+> -                       .flags = CLK_SET_RATE_GATE,
 >                 },
 >         }
 >  };
-> diff --git a/drivers/clk/qcom/gcc-msm8660.c b/drivers/clk/qcom/gcc-msm866=
-0.c
+> diff --git a/drivers/clk/qcom/gcc-msm8660.c b/drivers/clk/qcom/gcc-msm8660.c
 > index c347a0d44bc8..7e930e25c79f 100644
 > --- a/drivers/clk/qcom/gcc-msm8660.c
 > +++ b/drivers/clk/qcom/gcc-msm8660.c
-> @@ -1558,7 +1558,6 @@ static struct clk_rcg sdc1_src =3D {
->                         .parent_names =3D gcc_pxo_pll8,
->                         .num_parents =3D 2,
->                         .ops =3D &clk_rcg_ops,
-> -                       .flags =3D CLK_SET_RATE_GATE,
+> @@ -1558,7 +1558,6 @@ static struct clk_rcg sdc1_src = {
+>                         .parent_names = gcc_pxo_pll8,
+>                         .num_parents = 2,
+>                         .ops = &clk_rcg_ops,
+> -                       .flags = CLK_SET_RATE_GATE,
 >                 },
 >         }
 >  };
-> @@ -1607,7 +1606,6 @@ static struct clk_rcg sdc2_src =3D {
->                         .parent_names =3D gcc_pxo_pll8,
->                         .num_parents =3D 2,
->                         .ops =3D &clk_rcg_ops,
-> -                       .flags =3D CLK_SET_RATE_GATE,
+> @@ -1607,7 +1606,6 @@ static struct clk_rcg sdc2_src = {
+>                         .parent_names = gcc_pxo_pll8,
+>                         .num_parents = 2,
+>                         .ops = &clk_rcg_ops,
+> -                       .flags = CLK_SET_RATE_GATE,
 >                 },
 >         }
 >  };
-> @@ -1656,7 +1654,6 @@ static struct clk_rcg sdc3_src =3D {
->                         .parent_names =3D gcc_pxo_pll8,
->                         .num_parents =3D 2,
->                         .ops =3D &clk_rcg_ops,
-> -                       .flags =3D CLK_SET_RATE_GATE,
+> @@ -1656,7 +1654,6 @@ static struct clk_rcg sdc3_src = {
+>                         .parent_names = gcc_pxo_pll8,
+>                         .num_parents = 2,
+>                         .ops = &clk_rcg_ops,
+> -                       .flags = CLK_SET_RATE_GATE,
 >                 },
 >         }
 >  };
-> @@ -1705,7 +1702,6 @@ static struct clk_rcg sdc4_src =3D {
->                         .parent_names =3D gcc_pxo_pll8,
->                         .num_parents =3D 2,
->                         .ops =3D &clk_rcg_ops,
-> -                       .flags =3D CLK_SET_RATE_GATE,
+> @@ -1705,7 +1702,6 @@ static struct clk_rcg sdc4_src = {
+>                         .parent_names = gcc_pxo_pll8,
+>                         .num_parents = 2,
+>                         .ops = &clk_rcg_ops,
+> -                       .flags = CLK_SET_RATE_GATE,
 >                 },
 >         }
 >  };
-> @@ -1754,7 +1750,6 @@ static struct clk_rcg sdc5_src =3D {
->                         .parent_names =3D gcc_pxo_pll8,
->                         .num_parents =3D 2,
->                         .ops =3D &clk_rcg_ops,
-> -                       .flags =3D CLK_SET_RATE_GATE,
+> @@ -1754,7 +1750,6 @@ static struct clk_rcg sdc5_src = {
+>                         .parent_names = gcc_pxo_pll8,
+>                         .num_parents = 2,
+>                         .ops = &clk_rcg_ops,
+> -                       .flags = CLK_SET_RATE_GATE,
 >                 },
 >         }
 >  };
-> diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm896=
-0.c
+> diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c
 > index eb551c75fba6..fd495e0471bb 100644
 > --- a/drivers/clk/qcom/gcc-msm8960.c
 > +++ b/drivers/clk/qcom/gcc-msm8960.c
-> @@ -1628,7 +1628,6 @@ static struct clk_rcg sdc1_src =3D {
->                         .parent_names =3D gcc_pxo_pll8,
->                         .num_parents =3D 2,
->                         .ops =3D &clk_rcg_ops,
-> -                       .flags =3D CLK_SET_RATE_GATE,
+> @@ -1628,7 +1628,6 @@ static struct clk_rcg sdc1_src = {
+>                         .parent_names = gcc_pxo_pll8,
+>                         .num_parents = 2,
+>                         .ops = &clk_rcg_ops,
+> -                       .flags = CLK_SET_RATE_GATE,
 >                 },
 >         }
 >  };
-> @@ -1677,7 +1676,6 @@ static struct clk_rcg sdc2_src =3D {
->                         .parent_names =3D gcc_pxo_pll8,
->                         .num_parents =3D 2,
->                         .ops =3D &clk_rcg_ops,
-> -                       .flags =3D CLK_SET_RATE_GATE,
+> @@ -1677,7 +1676,6 @@ static struct clk_rcg sdc2_src = {
+>                         .parent_names = gcc_pxo_pll8,
+>                         .num_parents = 2,
+>                         .ops = &clk_rcg_ops,
+> -                       .flags = CLK_SET_RATE_GATE,
 >                 },
 >         }
 >  };
-> @@ -1726,7 +1724,6 @@ static struct clk_rcg sdc3_src =3D {
->                         .parent_names =3D gcc_pxo_pll8,
->                         .num_parents =3D 2,
->                         .ops =3D &clk_rcg_ops,
-> -                       .flags =3D CLK_SET_RATE_GATE,
+> @@ -1726,7 +1724,6 @@ static struct clk_rcg sdc3_src = {
+>                         .parent_names = gcc_pxo_pll8,
+>                         .num_parents = 2,
+>                         .ops = &clk_rcg_ops,
+> -                       .flags = CLK_SET_RATE_GATE,
 >                 },
 >         }
 >  };
-> @@ -1775,7 +1772,6 @@ static struct clk_rcg sdc4_src =3D {
->                         .parent_names =3D gcc_pxo_pll8,
->                         .num_parents =3D 2,
->                         .ops =3D &clk_rcg_ops,
-> -                       .flags =3D CLK_SET_RATE_GATE,
+> @@ -1775,7 +1772,6 @@ static struct clk_rcg sdc4_src = {
+>                         .parent_names = gcc_pxo_pll8,
+>                         .num_parents = 2,
+>                         .ops = &clk_rcg_ops,
+> -                       .flags = CLK_SET_RATE_GATE,
 >                 },
 >         }
 >  };
-> @@ -1824,7 +1820,6 @@ static struct clk_rcg sdc5_src =3D {
->                         .parent_names =3D gcc_pxo_pll8,
->                         .num_parents =3D 2,
->                         .ops =3D &clk_rcg_ops,
-> -                       .flags =3D CLK_SET_RATE_GATE,
+> @@ -1824,7 +1820,6 @@ static struct clk_rcg sdc5_src = {
+>                         .parent_names = gcc_pxo_pll8,
+>                         .num_parents = 2,
+>                         .ops = &clk_rcg_ops,
+> -                       .flags = CLK_SET_RATE_GATE,
 >                 },
 >         }
 >  };
-> -- =
-
+> -- 
 > 2.14.3
->=20
+>
diff --git a/a/content_digest b/N1/content_digest
index 7397198..c24e3ef 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -20,18 +20,15 @@
  "> the mmci driver (drivers/mmc/host/mmci.c) does the following sequence:\n"
  "> * clk_prepare_enable()\n"
  "> * clk_set_rate()\n"
- "> =\n"
- "\n"
+ "> \n"
  "> on SDCx_clk which is a children of SDCx_src. SDCx_src has\n"
  "> CLK_SET_RATE_GATE so this sequence should not be allowed but this was not\n"
  "> enforced. IOW, the flag is ignored. Dropping the flag won't change\n"
  "> anything to the current behaviour of the platform.\n"
- "> =\n"
- "\n"
+ "> \n"
  "> CLK_SET_RATE_GATE is being fixed and enforced now. If the flag was kept,\n"
  "> the mmci driver would receive -EBUSY when calling clk_set_rate()\n"
- "> =\n"
- "\n"
+ "> \n"
  "> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>\n"
  "\n"
  "Applied to clk-qcom-set-rate-gate.\n"
@@ -45,151 +42,145 @@
  ">  drivers/clk/qcom/gcc-msm8660.c | 5 -----\n"
  ">  drivers/clk/qcom/gcc-msm8960.c | 5 -----\n"
  ">  4 files changed, 15 deletions(-)\n"
- "> =\n"
- "\n"
- "> diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806=\n"
- "x.c\n"
+ "> \n"
+ "> diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c\n"
  "> index 28eb200d0f1e..5f61225657ab 100644\n"
  "> --- a/drivers/clk/qcom/gcc-ipq806x.c\n"
  "> +++ b/drivers/clk/qcom/gcc-ipq806x.c\n"
- "> @@ -1220,7 +1220,6 @@ static struct clk_rcg sdc1_src =3D {\n"
- ">                         .parent_names =3D gcc_pxo_pll8,\n"
- ">                         .num_parents =3D 2,\n"
- ">                         .ops =3D &clk_rcg_ops,\n"
- "> -                       .flags =3D CLK_SET_RATE_GATE,\n"
+ "> @@ -1220,7 +1220,6 @@ static struct clk_rcg sdc1_src = {\n"
+ ">                         .parent_names = gcc_pxo_pll8,\n"
+ ">                         .num_parents = 2,\n"
+ ">                         .ops = &clk_rcg_ops,\n"
+ "> -                       .flags = CLK_SET_RATE_GATE,\n"
  ">                 },\n"
  ">         }\n"
  ">  };\n"
- "> @@ -1269,7 +1268,6 @@ static struct clk_rcg sdc3_src =3D {\n"
- ">                         .parent_names =3D gcc_pxo_pll8,\n"
- ">                         .num_parents =3D 2,\n"
- ">                         .ops =3D &clk_rcg_ops,\n"
- "> -                       .flags =3D CLK_SET_RATE_GATE,\n"
+ "> @@ -1269,7 +1268,6 @@ static struct clk_rcg sdc3_src = {\n"
+ ">                         .parent_names = gcc_pxo_pll8,\n"
+ ">                         .num_parents = 2,\n"
+ ">                         .ops = &clk_rcg_ops,\n"
+ "> -                       .flags = CLK_SET_RATE_GATE,\n"
  ">                 },\n"
  ">         }\n"
  ">  };\n"
- "> @@ -1353,7 +1351,6 @@ static struct clk_rcg tsif_ref_src =3D {\n"
- ">                         .parent_names =3D gcc_pxo_pll8,\n"
- ">                         .num_parents =3D 2,\n"
- ">                         .ops =3D &clk_rcg_ops,\n"
- "> -                       .flags =3D CLK_SET_RATE_GATE,\n"
+ "> @@ -1353,7 +1351,6 @@ static struct clk_rcg tsif_ref_src = {\n"
+ ">                         .parent_names = gcc_pxo_pll8,\n"
+ ">                         .num_parents = 2,\n"
+ ">                         .ops = &clk_rcg_ops,\n"
+ "> -                       .flags = CLK_SET_RATE_GATE,\n"
  ">                 },\n"
  ">         }\n"
  ">  };\n"
- "> diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm961=\n"
- "5.c\n"
+ "> diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c\n"
  "> index b99dd406e907..849046fbed6d 100644\n"
  "> --- a/drivers/clk/qcom/gcc-mdm9615.c\n"
  "> +++ b/drivers/clk/qcom/gcc-mdm9615.c\n"
- "> @@ -947,7 +947,6 @@ static struct clk_rcg sdc1_src =3D {\n"
- ">                         .parent_names =3D gcc_cxo_pll8,\n"
- ">                         .num_parents =3D 2,\n"
- ">                         .ops =3D &clk_rcg_ops,\n"
- "> -                       .flags =3D CLK_SET_RATE_GATE,\n"
+ "> @@ -947,7 +947,6 @@ static struct clk_rcg sdc1_src = {\n"
+ ">                         .parent_names = gcc_cxo_pll8,\n"
+ ">                         .num_parents = 2,\n"
+ ">                         .ops = &clk_rcg_ops,\n"
+ "> -                       .flags = CLK_SET_RATE_GATE,\n"
  ">                 },\n"
  ">         }\n"
  ">  };\n"
- "> @@ -996,7 +995,6 @@ static struct clk_rcg sdc2_src =3D {\n"
- ">                         .parent_names =3D gcc_cxo_pll8,\n"
- ">                         .num_parents =3D 2,\n"
- ">                         .ops =3D &clk_rcg_ops,\n"
- "> -                       .flags =3D CLK_SET_RATE_GATE,\n"
+ "> @@ -996,7 +995,6 @@ static struct clk_rcg sdc2_src = {\n"
+ ">                         .parent_names = gcc_cxo_pll8,\n"
+ ">                         .num_parents = 2,\n"
+ ">                         .ops = &clk_rcg_ops,\n"
+ "> -                       .flags = CLK_SET_RATE_GATE,\n"
  ">                 },\n"
  ">         }\n"
  ">  };\n"
- "> diff --git a/drivers/clk/qcom/gcc-msm8660.c b/drivers/clk/qcom/gcc-msm866=\n"
- "0.c\n"
+ "> diff --git a/drivers/clk/qcom/gcc-msm8660.c b/drivers/clk/qcom/gcc-msm8660.c\n"
  "> index c347a0d44bc8..7e930e25c79f 100644\n"
  "> --- a/drivers/clk/qcom/gcc-msm8660.c\n"
  "> +++ b/drivers/clk/qcom/gcc-msm8660.c\n"
- "> @@ -1558,7 +1558,6 @@ static struct clk_rcg sdc1_src =3D {\n"
- ">                         .parent_names =3D gcc_pxo_pll8,\n"
- ">                         .num_parents =3D 2,\n"
- ">                         .ops =3D &clk_rcg_ops,\n"
- "> -                       .flags =3D CLK_SET_RATE_GATE,\n"
+ "> @@ -1558,7 +1558,6 @@ static struct clk_rcg sdc1_src = {\n"
+ ">                         .parent_names = gcc_pxo_pll8,\n"
+ ">                         .num_parents = 2,\n"
+ ">                         .ops = &clk_rcg_ops,\n"
+ "> -                       .flags = CLK_SET_RATE_GATE,\n"
  ">                 },\n"
  ">         }\n"
  ">  };\n"
- "> @@ -1607,7 +1606,6 @@ static struct clk_rcg sdc2_src =3D {\n"
- ">                         .parent_names =3D gcc_pxo_pll8,\n"
- ">                         .num_parents =3D 2,\n"
- ">                         .ops =3D &clk_rcg_ops,\n"
- "> -                       .flags =3D CLK_SET_RATE_GATE,\n"
+ "> @@ -1607,7 +1606,6 @@ static struct clk_rcg sdc2_src = {\n"
+ ">                         .parent_names = gcc_pxo_pll8,\n"
+ ">                         .num_parents = 2,\n"
+ ">                         .ops = &clk_rcg_ops,\n"
+ "> -                       .flags = CLK_SET_RATE_GATE,\n"
  ">                 },\n"
  ">         }\n"
  ">  };\n"
- "> @@ -1656,7 +1654,6 @@ static struct clk_rcg sdc3_src =3D {\n"
- ">                         .parent_names =3D gcc_pxo_pll8,\n"
- ">                         .num_parents =3D 2,\n"
- ">                         .ops =3D &clk_rcg_ops,\n"
- "> -                       .flags =3D CLK_SET_RATE_GATE,\n"
+ "> @@ -1656,7 +1654,6 @@ static struct clk_rcg sdc3_src = {\n"
+ ">                         .parent_names = gcc_pxo_pll8,\n"
+ ">                         .num_parents = 2,\n"
+ ">                         .ops = &clk_rcg_ops,\n"
+ "> -                       .flags = CLK_SET_RATE_GATE,\n"
  ">                 },\n"
  ">         }\n"
  ">  };\n"
- "> @@ -1705,7 +1702,6 @@ static struct clk_rcg sdc4_src =3D {\n"
- ">                         .parent_names =3D gcc_pxo_pll8,\n"
- ">                         .num_parents =3D 2,\n"
- ">                         .ops =3D &clk_rcg_ops,\n"
- "> -                       .flags =3D CLK_SET_RATE_GATE,\n"
+ "> @@ -1705,7 +1702,6 @@ static struct clk_rcg sdc4_src = {\n"
+ ">                         .parent_names = gcc_pxo_pll8,\n"
+ ">                         .num_parents = 2,\n"
+ ">                         .ops = &clk_rcg_ops,\n"
+ "> -                       .flags = CLK_SET_RATE_GATE,\n"
  ">                 },\n"
  ">         }\n"
  ">  };\n"
- "> @@ -1754,7 +1750,6 @@ static struct clk_rcg sdc5_src =3D {\n"
- ">                         .parent_names =3D gcc_pxo_pll8,\n"
- ">                         .num_parents =3D 2,\n"
- ">                         .ops =3D &clk_rcg_ops,\n"
- "> -                       .flags =3D CLK_SET_RATE_GATE,\n"
+ "> @@ -1754,7 +1750,6 @@ static struct clk_rcg sdc5_src = {\n"
+ ">                         .parent_names = gcc_pxo_pll8,\n"
+ ">                         .num_parents = 2,\n"
+ ">                         .ops = &clk_rcg_ops,\n"
+ "> -                       .flags = CLK_SET_RATE_GATE,\n"
  ">                 },\n"
  ">         }\n"
  ">  };\n"
- "> diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm896=\n"
- "0.c\n"
+ "> diff --git a/drivers/clk/qcom/gcc-msm8960.c b/drivers/clk/qcom/gcc-msm8960.c\n"
  "> index eb551c75fba6..fd495e0471bb 100644\n"
  "> --- a/drivers/clk/qcom/gcc-msm8960.c\n"
  "> +++ b/drivers/clk/qcom/gcc-msm8960.c\n"
- "> @@ -1628,7 +1628,6 @@ static struct clk_rcg sdc1_src =3D {\n"
- ">                         .parent_names =3D gcc_pxo_pll8,\n"
- ">                         .num_parents =3D 2,\n"
- ">                         .ops =3D &clk_rcg_ops,\n"
- "> -                       .flags =3D CLK_SET_RATE_GATE,\n"
+ "> @@ -1628,7 +1628,6 @@ static struct clk_rcg sdc1_src = {\n"
+ ">                         .parent_names = gcc_pxo_pll8,\n"
+ ">                         .num_parents = 2,\n"
+ ">                         .ops = &clk_rcg_ops,\n"
+ "> -                       .flags = CLK_SET_RATE_GATE,\n"
  ">                 },\n"
  ">         }\n"
  ">  };\n"
- "> @@ -1677,7 +1676,6 @@ static struct clk_rcg sdc2_src =3D {\n"
- ">                         .parent_names =3D gcc_pxo_pll8,\n"
- ">                         .num_parents =3D 2,\n"
- ">                         .ops =3D &clk_rcg_ops,\n"
- "> -                       .flags =3D CLK_SET_RATE_GATE,\n"
+ "> @@ -1677,7 +1676,6 @@ static struct clk_rcg sdc2_src = {\n"
+ ">                         .parent_names = gcc_pxo_pll8,\n"
+ ">                         .num_parents = 2,\n"
+ ">                         .ops = &clk_rcg_ops,\n"
+ "> -                       .flags = CLK_SET_RATE_GATE,\n"
  ">                 },\n"
  ">         }\n"
  ">  };\n"
- "> @@ -1726,7 +1724,6 @@ static struct clk_rcg sdc3_src =3D {\n"
- ">                         .parent_names =3D gcc_pxo_pll8,\n"
- ">                         .num_parents =3D 2,\n"
- ">                         .ops =3D &clk_rcg_ops,\n"
- "> -                       .flags =3D CLK_SET_RATE_GATE,\n"
+ "> @@ -1726,7 +1724,6 @@ static struct clk_rcg sdc3_src = {\n"
+ ">                         .parent_names = gcc_pxo_pll8,\n"
+ ">                         .num_parents = 2,\n"
+ ">                         .ops = &clk_rcg_ops,\n"
+ "> -                       .flags = CLK_SET_RATE_GATE,\n"
  ">                 },\n"
  ">         }\n"
  ">  };\n"
- "> @@ -1775,7 +1772,6 @@ static struct clk_rcg sdc4_src =3D {\n"
- ">                         .parent_names =3D gcc_pxo_pll8,\n"
- ">                         .num_parents =3D 2,\n"
- ">                         .ops =3D &clk_rcg_ops,\n"
- "> -                       .flags =3D CLK_SET_RATE_GATE,\n"
+ "> @@ -1775,7 +1772,6 @@ static struct clk_rcg sdc4_src = {\n"
+ ">                         .parent_names = gcc_pxo_pll8,\n"
+ ">                         .num_parents = 2,\n"
+ ">                         .ops = &clk_rcg_ops,\n"
+ "> -                       .flags = CLK_SET_RATE_GATE,\n"
  ">                 },\n"
  ">         }\n"
  ">  };\n"
- "> @@ -1824,7 +1820,6 @@ static struct clk_rcg sdc5_src =3D {\n"
- ">                         .parent_names =3D gcc_pxo_pll8,\n"
- ">                         .num_parents =3D 2,\n"
- ">                         .ops =3D &clk_rcg_ops,\n"
- "> -                       .flags =3D CLK_SET_RATE_GATE,\n"
+ "> @@ -1824,7 +1820,6 @@ static struct clk_rcg sdc5_src = {\n"
+ ">                         .parent_names = gcc_pxo_pll8,\n"
+ ">                         .num_parents = 2,\n"
+ ">                         .ops = &clk_rcg_ops,\n"
+ "> -                       .flags = CLK_SET_RATE_GATE,\n"
  ">                 },\n"
  ">         }\n"
  ">  };\n"
- "> -- =\n"
- "\n"
+ "> -- \n"
  "> 2.14.3\n"
- >=20
+ >
 
-fa489ad7c063c34473df897345b504d2af73294a801cb360a78e8a769f792cf5
+e98228ebe97bcf1394d066190a77d2f6045b89e993bf9fa67397b9ee53f05bcd

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