From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (146.0.238.70:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 20 Jun 2018 20:13:15 -0000 Received: from mga06.intel.com ([134.134.136.31]) by Galois.linutronix.de with esmtps (TLS1.2:DHE_RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1fVjTc-0003JQ-Do for speck@linutronix.de; Wed, 20 Jun 2018 22:13:14 +0200 Date: Wed, 20 Jun 2018 13:13:09 -0700 From: Andi Kleen Subject: [MODERATED] Re: [PATCH 1/2] L1TF KVM v2 1 Message-ID: <20180620201309.GR30690@tassilo.jf.intel.com> References: <20180620164207.31771-1-pbonzini@redhat.com> <20180620164207.31771-2-pbonzini@redhat.com> MIME-Version: 1.0 In-Reply-To: <20180620164207.31771-2-pbonzini@redhat.com> Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: > + > +/* > + * The L1D cache is 32 KiB on Skylake, but to flush it we have to read in > + * 64 KiB because the replacement algorithm is not exactly LRU. > + */ > +#define L1D_CACHE_ORDER 4 > +static void *__read_mostly empty_zero_pages; I thought we agreed to remove this? We should be only using the MSR based flush methods, as microcode updates are needed in any case for other things. -Andi