From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (146.0.238.70:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 20 Jun 2018 20:32:10 -0000 Received: from aserp2120.oracle.com ([141.146.126.78]) by Galois.linutronix.de with esmtps (TLS1.2:RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1fVjlx-0003hl-9o for speck@linutronix.de; Wed, 20 Jun 2018 22:32:09 +0200 Received: from pps.filterd (aserp2120.oracle.com [127.0.0.1]) by aserp2120.oracle.com (8.16.0.22/8.16.0.22) with SMTP id w5KKTCOF029989 for ; Wed, 20 Jun 2018 20:32:02 GMT Received: from userv0022.oracle.com (userv0022.oracle.com [156.151.31.74]) by aserp2120.oracle.com with ESMTP id 2jmtgwx5bs-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Wed, 20 Jun 2018 20:32:02 +0000 Received: from aserv0121.oracle.com (aserv0121.oracle.com [141.146.126.235]) by userv0022.oracle.com (8.14.4/8.14.4) with ESMTP id w5KKW1gX029886 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Wed, 20 Jun 2018 20:32:01 GMT Received: from abhmp0010.oracle.com (abhmp0010.oracle.com [141.146.116.16]) by aserv0121.oracle.com (8.14.4/8.13.8) with ESMTP id w5KKW1lA001114 for ; Wed, 20 Jun 2018 20:32:01 GMT Date: Wed, 20 Jun 2018 16:32:00 -0400 From: Konrad Rzeszutek Wilk Subject: [MODERATED] Re: [PATCH 2/2] L1TF KVM v2 2 Message-ID: <20180620203200.GC28309@char.us.oracle.com> References: <20180620164207.31771-1-pbonzini@redhat.com> <20180620164207.31771-3-pbonzini@redhat.com> MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Wed, Jun 20, 2018 at 10:25:45PM +0200, speck for Jiri Kosina wrote: > On Wed, 20 Jun 2018, speck for Paolo Bonzini wrote: > > > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h > > index 578793e97431..aebf89c4175d 100644 > > --- a/arch/x86/include/asm/cpufeatures.h > > +++ b/arch/x86/include/asm/cpufeatures.h > > @@ -333,6 +333,7 @@ > > #define X86_FEATURE_PCONFIG (18*32+18) /* Intel PCONFIG */ > > #define X86_FEATURE_SPEC_CTRL (18*32+26) /* "" Speculation Control (IBRS + IBPB) */ > > #define X86_FEATURE_INTEL_STIBP (18*32+27) /* "" Single Thread Indirect Branch Predictors */ > > +#define X86_FEATURE_FLUSH_L1D (18*32+28) /* IA32_FLUSH_L1D MSR */ > > #define X86_FEATURE_ARCH_CAPABILITIES (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */ > > > > /* > > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h > > index 53d5b1b9255e..f43bd9f23053 100644 > > --- a/arch/x86/include/asm/msr-index.h > > +++ b/arch/x86/include/asm/msr-index.h > > @@ -65,6 +65,9 @@ > > > > #define MSR_MTRRcap 0x000000fe > > > > +#define MSR_IA32_FLUSH_L1D 0x10b > > +#define MSR_IA32_FLUSH_L1D_VALUE 0x00000001 > > + > > #define MSR_IA32_ARCH_CAPABILITIES 0x0000010a > > #define ARCH_CAP_RDCL_NO (1 << 0) /* Not susceptible to Meltdown */ > > #define ARCH_CAP_IBRS_ALL (1 << 1) /* Enhanced IBRS support */ > > diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c > > index 8bf8f672cece..c88ed554bb66 100644 > > --- a/arch/x86/kvm/x86.c > > +++ b/arch/x86/kvm/x86.c > > @@ -6551,8 +6551,15 @@ static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused, > > > > void kvm_l1d_flush(void) > > { > > + int size; > > + > > + if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) { > > Umm, where exactly do you set this feature bit? CPUID.7 array ends up being set automatically in cpu/common.c. > > Thanks, > > -- > Jiri Kosina > SUSE Labs