From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (146.0.238.70:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 20 Jun 2018 20:49:36 -0000 Received: from aserp2120.oracle.com ([141.146.126.78]) by Galois.linutronix.de with esmtps (TLS1.2:RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1fVk0G-0004T1-0k for speck@linutronix.de; Wed, 20 Jun 2018 22:46:56 +0200 Received: from pps.filterd (aserp2120.oracle.com [127.0.0.1]) by aserp2120.oracle.com (8.16.0.22/8.16.0.22) with SMTP id w5KKi9wg039820 for ; Wed, 20 Jun 2018 20:46:49 GMT Received: from aserv0022.oracle.com (aserv0022.oracle.com [141.146.126.234]) by aserp2120.oracle.com with ESMTP id 2jmtgwx6mg-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Wed, 20 Jun 2018 20:46:49 +0000 Received: from userv0122.oracle.com (userv0122.oracle.com [156.151.31.75]) by aserv0022.oracle.com (8.14.4/8.14.4) with ESMTP id w5KKkmd9011098 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Wed, 20 Jun 2018 20:46:48 GMT Received: from abhmp0007.oracle.com (abhmp0007.oracle.com [141.146.116.13]) by userv0122.oracle.com (8.14.4/8.14.4) with ESMTP id w5KKkmWc007441 for ; Wed, 20 Jun 2018 20:46:48 GMT Message-Id: <20180620204255.997582191@localhost.localdomain> Date: Wed, 20 Jun 2018 16:42:56 -0400 From: konrad.wilk@oracle.com Subject: [MODERATED] [PATCH v2.1 0/6] On top of Thomas+Paolo's Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit MIME-Version: 1.0 To: speck@linutronix.de List-ID: Hey, This patchset replaces Paolo's second patch but also adds the warnings that Linus wanted. Along with some extra knobs in case the MSR will have more things in the future. Oh, and one bug-fix. I am also working on using the VMX Load MSR list so that the L1D flush happens automatically on VMENTER. Konrad Rzeszutek Wilk (5): x86/bugs: Move the l1tf function and define pr_fmt properly x86/cpufeatures: Add detection of L1D cache flush support. x86/bugs: Read FLUSH_CMD MSR during boot. x86/KVM: Warn user if KVM is loaded SMT and L1TF CPU bug being present. x86/KVM: Use L1 cache flush before VMENTER if available. Paolo Bonzini (1): kvm: x86: mitigation for L1 cache terminal fault vulnerabilities Documentation/admin-guide/kernel-parameters.txt | 4 ++ arch/x86/include/asm/cpu.h | 4 ++ arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/kvm_host.h | 7 ++- arch/x86/include/asm/msr-index.h | 6 ++ arch/x86/kernel/cpu/bugs.c | 83 +++++++++++++++++-------- arch/x86/kvm/mmu.c | 1 + arch/x86/kvm/svm.c | 3 +- arch/x86/kvm/vmx.c | 46 +++++++++++++- arch/x86/kvm/x86.c | 80 +++++++++++++++++++++++- kernel/cpu.c | 1 + 11 files changed, 205 insertions(+), 31 deletions(-)