From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (146.0.238.70:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 21 Jun 2018 13:55:16 -0000 Received: from userp2120.oracle.com ([156.151.31.85]) by Galois.linutronix.de with esmtps (TLS1.2:RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1fW03N-0008GL-Ms for speck@linutronix.de; Thu, 21 Jun 2018 15:55:14 +0200 Received: from pps.filterd (userp2120.oracle.com [127.0.0.1]) by userp2120.oracle.com (8.16.0.22/8.16.0.22) with SMTP id w5LDsWpU070143 for ; Thu, 21 Jun 2018 13:55:07 GMT Received: from userv0021.oracle.com (userv0021.oracle.com [156.151.31.71]) by userp2120.oracle.com with ESMTP id 2jmu6y0tfu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Thu, 21 Jun 2018 13:55:07 +0000 Received: from userv0121.oracle.com (userv0121.oracle.com [156.151.31.72]) by userv0021.oracle.com (8.14.4/8.14.4) with ESMTP id w5LDt6Dl009977 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Thu, 21 Jun 2018 13:55:06 GMT Received: from abhmp0011.oracle.com (abhmp0011.oracle.com [141.146.116.17]) by userv0121.oracle.com (8.14.4/8.13.8) with ESMTP id w5LDt68N018549 for ; Thu, 21 Jun 2018 13:55:06 GMT Date: Thu, 21 Jun 2018 09:55:05 -0400 From: Konrad Rzeszutek Wilk Subject: [MODERATED] Re: [PATCH v2.1 3/6] [PATCH v2.1 3/6] Patch #3 Message-ID: <20180621135505.GC28543@char.US.ORACLE.com> References: <20180620204351.930346665@localhost.localdomain> <20180621031623.GB9544@char.us.oracle.com> MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Thu, Jun 21, 2018 at 09:58:32AM +0200, speck for Thomas Gleixner wrote: > On Wed, 20 Jun 2018, speck for Konrad Rzeszutek Wilk wrote: > > > diff --git a/arch/x86/kernel/cpu/bugs.c b/arch/x86/kernel/cpu/bugs.c > > > index 50500cea6eba..659963bf9a3c 100644 > > > --- a/arch/x86/kernel/cpu/bugs.c > > > +++ b/arch/x86/kernel/cpu/bugs.c > > > @@ -53,6 +53,13 @@ static u64 __ro_after_init x86_spec_ctrl_mask = SPEC_CTRL_IBRS; > > > u64 __ro_after_init x86_amd_ls_cfg_base; > > > u64 __ro_after_init x86_amd_ls_cfg_ssbd_mask; > > > > > > +/* > > > + * Our boot-time value of the IA32_FLUSH_CMD MSR. We read it once so that > > > + * any writes to the IA32_FLUSH_CMD contain whatever reserved bits have been > > > + * set. > > > + */ > > > +static u64 __ro_after_init x86_flush_cmd; > > > + > > > void __init check_bugs(void) > > > { > > > identify_boot_cpu(); > > > @@ -85,6 +92,10 @@ void __init check_bugs(void) > > > > > > l1tf_select_mitigation(); > > > > > > + /* Similar to SPEC_CTRL MSR, read it to account for reserved bits. */ > > > + if (boot_cpu_has(X86_FEATURE_FLUSH_L1D)) > > > + rdmsrl(MSR_IA32_FLUSH_CMD, x86_flush_cmd); > > > > > > The spec didn't mention it but the development microcode I am assuming looks to be a > > write-only MSR, so I changed this to: > > > > (void)rdmsrl_safe(MSR_IA32_FLUSH_CMD, &x86_flush_cmd); > > Which is pointless as my version of that magic PDF clearly says: > > New MSR IA32_FLUSH_CMD (MSR 0x10B, Write-only) bit 0: L1D Flush Duh. Indeed. > > Thanks, > > tglx