From: Andrea Parri <andrea.parri@amarulasolutions.com>
To: Will Deacon <will.deacon@arm.com>
Cc: Peter Zijlstra <peterz@infradead.org>,
Alan Stern <stern@rowland.harvard.edu>,
LKMM Maintainers -- Akira Yokosawa <akiyks@gmail.com>,
Boqun Feng <boqun.feng@gmail.com>,
David Howells <dhowells@redhat.com>,
Jade Alglave <j.alglave@ucl.ac.uk>,
Luc Maranget <luc.maranget@inria.fr>,
Nicholas Piggin <npiggin@gmail.com>,
"Paul E. McKenney" <paulmck@linux.vnet.ibm.com>,
Kernel development list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 2/2] tools/memory-model: Add write ordering by release-acquire and by locks
Date: Fri, 22 Jun 2018 13:25:53 +0200 [thread overview]
Message-ID: <20180622112553.GA10658@andrea> (raw)
In-Reply-To: <20180622103838.GF7601@arm.com>
> > > I also just realised that this prevents Power from using ctrl+isync to
> > > implement acquire, should they wish to do so.
> >
> > They in fact do so on chips lacking LWSYNC, see how PPC_ACQUIRE_BARRIER
> > (as used by atomic_*_acquire) turns into ISYNC (note however that they
> > do not use PPC_ACQUIRE_BARRIER for smp_load_acquire -- because there's
> > no CTRL there).
>
> Right, so the example in the commit message is broken on PPC then. I think
> it's also broken on RISC-V, despite the claim.
I agree for RISC-V (and I missed it in my earlier review): the 2nd
snippet from the commit message would map to something like
fence rw, w
STORE #1,[x]
LOAD [x]
fence r ,rw
STORE #1,[y]
and there would be no guarantee that the stores to x and y will be
propagated in program order to another CPU, AFAICT. Thank you for
pointing this out.
Andrea
next prev parent reply other threads:[~2018-06-22 11:26 UTC|newest]
Thread overview: 55+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-21 17:27 [PATCH 2/2] tools/memory-model: Add write ordering by release-acquire and by locks Alan Stern
2018-06-21 18:04 ` Peter Zijlstra
2018-06-22 3:34 ` Paul E. McKenney
2018-06-22 8:08 ` Peter Zijlstra
2018-06-22 8:09 ` Will Deacon
2018-06-22 9:55 ` Will Deacon
2018-06-22 10:31 ` Peter Zijlstra
2018-06-22 10:38 ` Will Deacon
2018-06-22 11:25 ` Andrea Parri [this message]
2018-06-22 16:40 ` Paul E. McKenney
2018-06-22 18:09 ` Alan Stern
2018-06-22 18:30 ` Will Deacon
2018-06-22 19:11 ` Alan Stern
2018-06-22 20:53 ` Paul E. McKenney
2018-07-04 11:53 ` Will Deacon
2018-06-25 8:19 ` Andrea Parri
2018-07-03 17:28 ` Alan Stern
2018-07-04 11:28 ` Paul E. McKenney
2018-07-04 12:13 ` Will Deacon
2018-07-05 14:23 ` Alan Stern
2018-07-05 15:31 ` Paul E. McKenney
2018-07-04 12:11 ` Will Deacon
2018-07-05 14:00 ` Andrea Parri
2018-07-05 14:44 ` Will Deacon
2018-07-05 15:16 ` Daniel Lustig
2018-07-05 15:35 ` Daniel Lustig
2018-07-05 14:21 ` Alan Stern
2018-07-05 14:46 ` Will Deacon
2018-07-05 14:57 ` Alan Stern
2018-07-05 15:15 ` Will Deacon
2018-07-05 15:09 ` Andrea Parri
2018-07-06 20:37 ` Alan Stern
2018-07-06 21:10 ` Paul E. McKenney
2018-07-09 16:52 ` Will Deacon
2018-07-09 17:29 ` Daniel Lustig
2018-07-09 19:18 ` Alan Stern
2018-07-05 15:31 ` Paul E. McKenney
2018-07-05 15:39 ` Andrea Parri
2018-07-05 16:58 ` Paul E. McKenney
2018-07-05 17:06 ` Andrea Parri
2018-07-05 15:44 ` Daniel Lustig
2018-07-05 16:22 ` Will Deacon
2018-07-05 16:56 ` Paul E. McKenney
2018-07-05 18:12 ` Daniel Lustig
2018-07-05 18:38 ` Andrea Parri
2018-07-05 18:44 ` Andrea Parri
2018-07-05 23:32 ` Paul E. McKenney
2018-07-05 23:31 ` Paul E. McKenney
2018-07-06 9:25 ` Will Deacon
2018-07-06 14:14 ` Paul E. McKenney
2018-06-25 7:32 ` Peter Zijlstra
2018-06-25 8:29 ` Andrea Parri
2018-06-25 9:06 ` Peter Zijlstra
2018-06-22 9:06 ` Andrea Parri
2018-06-22 19:23 ` Alan Stern
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