From: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
To: Stephen Boyd <swboyd-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>
Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
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chandanu-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org
Subject: Re: [PATCH v12 3/5] dt-bindings: drm/bridge: Document sn65dsi86 bridge bindings
Date: Mon, 25 Jun 2018 08:44:05 -0600 [thread overview]
Message-ID: <20180625144405.GA5864@rob-hp-laptop> (raw)
In-Reply-To: <152991040964.16708.10837173113497426796-n1Xw8LXHxjTHt/MElyovVYaSKrA+ACpX0E9HWUfgJXw@public.gmane.org>
On Mon, Jun 25, 2018 at 12:06:49AM -0700, Stephen Boyd wrote:
> Quoting spanda@codeaurora.org (2018-06-24 21:56:05)
> > On 2018-06-22 06:42, Stephen Boyd wrote:
> > > Quoting Sandeep Panda (2018-06-21 05:32:07)
> > >> + clock rate must be 12 MHz, 19.2 MHz, 26 MHz, 27 MHz or 38.4
> > >> MHz.
> > >> +
> > >> +- data-lanes: See ../../media/video-interface.txt
> > >> +- lane-polarities: See ../../media/video-interface.txt
> > >
> > > We need another property for suspend-gpios function of GPIO1. I suppose
> > > for the other GPIOs we don't need anything like this because they're
> > > output functions only? GPIO4 can do PWM and I guess if pwm is used in
> > > DT
> > > from here then the driver can mux that out of gpio4 properly. I have no
> > > idea how the hsync and vsync GPIOs would work though. I see that GPIO3
> > > can do DSIA hsync or vsync and GPIO2 can do DSIA vsync and I would
> > > guess
> > > those are in output mode only. Maybe that's just another property on
> > > this node to indicate if we should mux out the function or not. Usually
> > > that's done from pinctrl though. I don't have a use case for those
> > > functions but I do care about suspend gpios so at least add that one
> > > please.
> >
> > I was thinking of adding gpio1 (suspend-gpio) documentation when we add
> > support for PSR feature. Since for PSR we will be using this
> > suspoend-gpio.
> >
>
> Ok sure, but I don't see any harm in adding it now. I'm fine with
> waiting for the binding update when the PSR patches come if you feel
> like adding it now will delay something.
Please make the binding complete as possible now.
Rob
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next prev parent reply other threads:[~2018-06-25 14:44 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-21 12:32 [PATCH v12 0/5] Add suppport for sn65dsi86 bridge chip and Innolux 2k edp panel Sandeep Panda
[not found] ` <1529584329-632-1-git-send-email-spanda-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-06-21 12:32 ` [PATCH v12 1/5] dt-bindings: media: extend interface documentation for DSI and DP Sandeep Panda
2018-06-21 12:32 ` [PATCH v12 2/5] drm/bridge: add support for sn65dsi86 bridge driver Sandeep Panda
2018-06-21 12:32 ` [PATCH v12 3/5] dt-bindings: drm/bridge: Document sn65dsi86 bridge bindings Sandeep Panda
[not found] ` <1529584329-632-4-git-send-email-spanda-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-06-22 1:12 ` Stephen Boyd
[not found] ` <152962993355.16708.2310695895490918997-n1Xw8LXHxjTHt/MElyovVYaSKrA+ACpX0E9HWUfgJXw@public.gmane.org>
2018-06-25 4:56 ` spanda-sgV2jX0FEOL9JmXXK+q4OQ
[not found] ` <2110b47210e3caf6b747ae2297e24b33-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-06-25 7:06 ` Stephen Boyd
[not found] ` <152991040964.16708.10837173113497426796-n1Xw8LXHxjTHt/MElyovVYaSKrA+ACpX0E9HWUfgJXw@public.gmane.org>
2018-06-25 14:44 ` Rob Herring [this message]
2018-06-21 12:32 ` [PATCH v12 4/5] drm/panel: add Innolux TV123WAM panel driver support Sandeep Panda
2018-06-21 12:32 ` [PATCH v12 5/5] dt-bindings: drm/panel: Document Innolux TV123WAM panel bindings Sandeep Panda
2018-06-29 12:14 ` Andrzej Hajda
[not found] ` <20180629121414eucas1p21171a1eab3ee081c8b4114ca58264669~8oIIwEXJJ1824018240eucas1p2G-PmokGAFL9ItqW5MlFJXMulaTQe2KTcn/@public.gmane.org>
2018-07-05 6:38 ` spanda-sgV2jX0FEOL9JmXXK+q4OQ
2018-07-05 10:18 ` Andrzej Hajda
[not found] ` <20180705101827eucas1p2fcc767335aee02c1735e045ebefabc84~_cawUMmOH2040620406eucas1p22-PmokGAFL9ItqW5MlFJXMulaTQe2KTcn/@public.gmane.org>
2018-07-05 10:43 ` spanda-sgV2jX0FEOL9JmXXK+q4OQ
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