From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.linutronix.de (146.0.238.70:993) by crypto-ml.lab.linutronix.de with IMAP4-SSL for ; 27 Jun 2018 14:43:42 -0000 Received: from userp2120.oracle.com ([156.151.31.85]) by Galois.linutronix.de with esmtps (TLS1.2:RSA_AES_256_CBC_SHA256:256) (Exim 4.80) (envelope-from ) id 1fYBfZ-0006r0-4C for speck@linutronix.de; Wed, 27 Jun 2018 16:43:41 +0200 Received: from pps.filterd (userp2120.oracle.com [127.0.0.1]) by userp2120.oracle.com (8.16.0.22/8.16.0.22) with SMTP id w5REdqYQ131330 for ; Wed, 27 Jun 2018 14:43:34 GMT Received: from userv0022.oracle.com (userv0022.oracle.com [156.151.31.74]) by userp2120.oracle.com with ESMTP id 2jum0a551n-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Wed, 27 Jun 2018 14:43:34 +0000 Received: from userv0122.oracle.com (userv0122.oracle.com [156.151.31.75]) by userv0022.oracle.com (8.14.4/8.14.4) with ESMTP id w5REhXbP015588 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK) for ; Wed, 27 Jun 2018 14:43:33 GMT Received: from abhmp0008.oracle.com (abhmp0008.oracle.com [141.146.116.14]) by userv0122.oracle.com (8.14.4/8.14.4) with ESMTP id w5REhXCo012062 for ; Wed, 27 Jun 2018 14:43:33 GMT Date: Wed, 27 Jun 2018 10:43:26 -0400 From: Konrad Rzeszutek Wilk Subject: [MODERATED] Re: [PATCH v4 8/8] [PATCH v4 8/8] Linux Patch #8 Message-ID: <20180627144326.GD21873@char.US.ORACLE.com> References: <20180623135446.010873334@localhost.localdomain> MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: speck@linutronix.de List-ID: On Wed, Jun 27, 2018 at 03:05:02PM +0200, speck for Thomas Gleixner wrote: > On Sat, 23 Jun 2018, speck for konrad.wilk_at_oracle.com wrote: > > x86/KVM/VMX: Use MSR save list for IA32_FLUSH_CMD if required. > > + > > + /* > > + * If we enforce flushing the L1D cache on every VMENTER lets use the > > + * MSR save list. > > + */ > > + if (vmx_l1d_cache_flush_req(&vmx->vcpu)) > > + if (vmentry_l1d_flush == 2) > > + add_atomic_switch_msr(vmx, MSR_IA32_FLUSH_CMD, > > + L1D_FLUSH, 0, true); > > That's broken when the CPU does not have the FLUSH MSR, unless I'm missing > something. It should have the check for the static_cpu_has(X86_FEATURE_FLUSH_L1D). > > > static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event) > > @@ -10079,7 +10095,7 @@ static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu) > > evmcs_rsp = static_branch_unlikely(&enable_evmcs) ? > > (unsigned long)¤t_evmcs->host_rsp : 0; > > > > - if (vcpu->arch.flush_cache_req) > > + if (vcpu->arch.flush_cache_req && vmentry_l1d_flush != 1) > > kvm_l1d_flush(); > > Huch? So above you use the MSR list for vmentry_l1d_flush == 2 and here you > do the direct flush for vmentry_l1d_flush != 1. That should be == 1, right? Yes in fact I vividely remember fixing this up as my debug patch has this this extra logic (so that I could turn on/off the MSR list): if (vcpu->arch.flush_cache_req) { + if ((vmentry_l1d_flush == 2) && (!use_msr_save)) + kvm_l1d_flush(); + else if (vmentry_l1d_flush == 1) + kvm_l1d_flush(); and yet I managed to post the stale version. Arggh. > > Thanks, > > tglx