diff for duplicates of <20180627163749.GA8729@arm.com> diff --git a/a/1.txt b/N1/1.txt index 41869ef..aba5c76 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -1,7 +1,7 @@ Hi Vivek, On Tue, Jun 19, 2018 at 02:04:44PM +0530, Vivek Gautam wrote: -> On Fri, Jun 15, 2018 at 10:22 PM, Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> wrote: +> On Fri, Jun 15, 2018 at 10:22 PM, Will Deacon <will.deacon@arm.com> wrote: > > On Fri, Jun 15, 2018 at 04:23:29PM +0530, Vivek Gautam wrote: > >> Qualcomm SoCs have an additional level of cache called as > >> System cache or Last level cache[1]. This cache sits right diff --git a/a/content_digest b/N1/content_digest index 9b00a57..0ef66c3 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,24 +1,16 @@ "ref\020180615105329.26800-1-vivek.gautam@codeaurora.org\0" "ref\020180615165232.GE2202@arm.com\0" "ref\0CAFp+6iFm29ufb2Pr7Gb-2O_aN3GQLH4rcyWhbQGZ3QiwCC8vPg@mail.gmail.com\0" - "ref\0CAFp+6iFm29ufb2Pr7Gb-2O_aN3GQLH4rcyWhbQGZ3QiwCC8vPg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org\0" - "From\0Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>\0" - "Subject\0Re: [PATCH 1/1] iommu/arm-smmu: Add support to use Last level cache\0" + "From\0will.deacon@arm.com (Will Deacon)\0" + "Subject\0[PATCH 1/1] iommu/arm-smmu: Add support to use Last level cache\0" "Date\0Wed, 27 Jun 2018 17:37:50 +0100\0" - "To\0Vivek Gautam <vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>\0" - "Cc\0pdaly-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org" - linux-arm-msm <linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> - open list <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> - list-Y9sIeH5OGRo@public.gmane.org:IOMMU DRIVERS <iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org> - Joerg Roedel <joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org> - <iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org> - " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" + "To\0linux-arm-kernel@lists.infradead.org\0" "\00:1\0" "b\0" "Hi Vivek,\n" "\n" "On Tue, Jun 19, 2018 at 02:04:44PM +0530, Vivek Gautam wrote:\n" - "> On Fri, Jun 15, 2018 at 10:22 PM, Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> wrote:\n" + "> On Fri, Jun 15, 2018 at 10:22 PM, Will Deacon <will.deacon@arm.com> wrote:\n" "> > On Fri, Jun 15, 2018 at 04:23:29PM +0530, Vivek Gautam wrote:\n" "> >> Qualcomm SoCs have an additional level of cache called as\n" "> >> System cache or Last level cache[1]. This cache sits right\n" @@ -88,4 +80,4 @@ "\n" Will -9ef6237096eb5ebb09b25a14ce346729c42886c05f66be02b48f25d62c1b92e2 +aa551c37667feda80076f01bda6dc1313693749ad939b4c19a6494997eee8fc9
diff --git a/a/1.txt b/N2/1.txt index 41869ef..aba5c76 100644 --- a/a/1.txt +++ b/N2/1.txt @@ -1,7 +1,7 @@ Hi Vivek, On Tue, Jun 19, 2018 at 02:04:44PM +0530, Vivek Gautam wrote: -> On Fri, Jun 15, 2018 at 10:22 PM, Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> wrote: +> On Fri, Jun 15, 2018 at 10:22 PM, Will Deacon <will.deacon@arm.com> wrote: > > On Fri, Jun 15, 2018 at 04:23:29PM +0530, Vivek Gautam wrote: > >> Qualcomm SoCs have an additional level of cache called as > >> System cache or Last level cache[1]. This cache sits right diff --git a/a/content_digest b/N2/content_digest index 9b00a57..0a1ba95 100644 --- a/a/content_digest +++ b/N2/content_digest @@ -1,24 +1,27 @@ "ref\020180615105329.26800-1-vivek.gautam@codeaurora.org\0" "ref\020180615165232.GE2202@arm.com\0" "ref\0CAFp+6iFm29ufb2Pr7Gb-2O_aN3GQLH4rcyWhbQGZ3QiwCC8vPg@mail.gmail.com\0" - "ref\0CAFp+6iFm29ufb2Pr7Gb-2O_aN3GQLH4rcyWhbQGZ3QiwCC8vPg-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org\0" - "From\0Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org>\0" + "From\0Will Deacon <will.deacon@arm.com>\0" "Subject\0Re: [PATCH 1/1] iommu/arm-smmu: Add support to use Last level cache\0" "Date\0Wed, 27 Jun 2018 17:37:50 +0100\0" - "To\0Vivek Gautam <vivek.gautam-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>\0" - "Cc\0pdaly-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org" - linux-arm-msm <linux-arm-msm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> - open list <linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org> - list-Y9sIeH5OGRo@public.gmane.org:IOMMU DRIVERS <iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org> - Joerg Roedel <joro-zLv9SwRftAIdnm+yROfE0A@public.gmane.org> - <iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org> - " linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org\0" + "To\0Vivek Gautam <vivek.gautam@codeaurora.org>\0" + "Cc\0Robin Murphy <robin.murphy@arm.com>" + list@263.net:IOMMU DRIVERS <iommu@lists.linux-foundation.org> + Joerg Roedel <joro@8bytes.org> + <joro@8bytes.org> + linux-arm-kernel@lists.infradead.org + list@263.net:IOMMU DRIVERS <iommu@lists.linux-foundation.org> + Joerg Roedel <joro@8bytes.org> + <iommu@lists.linux-foundation.org> + open list <linux-kernel@vger.kernel.org> + linux-arm-msm <linux-arm-msm@vger.kernel.org> + " pdaly@codeaurora.org\0" "\00:1\0" "b\0" "Hi Vivek,\n" "\n" "On Tue, Jun 19, 2018 at 02:04:44PM +0530, Vivek Gautam wrote:\n" - "> On Fri, Jun 15, 2018 at 10:22 PM, Will Deacon <will.deacon-5wv7dgnIgG8@public.gmane.org> wrote:\n" + "> On Fri, Jun 15, 2018 at 10:22 PM, Will Deacon <will.deacon@arm.com> wrote:\n" "> > On Fri, Jun 15, 2018 at 04:23:29PM +0530, Vivek Gautam wrote:\n" "> >> Qualcomm SoCs have an additional level of cache called as\n" "> >> System cache or Last level cache[1]. This cache sits right\n" @@ -88,4 +91,4 @@ "\n" Will -9ef6237096eb5ebb09b25a14ce346729c42886c05f66be02b48f25d62c1b92e2 +fafa0bd0e062133e24b5ac945fa4f7afbbfced73b4fa068fe15ec4677cd1eb01
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.