From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Jani Nikula <jani.nikula@intel.com>
Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: Re: [PATCH] drm/i915: encourage BIT() macro usage in register definitions
Date: Wed, 27 Jun 2018 21:57:49 -0700 [thread overview]
Message-ID: <20180628045749.GH9765@intel.com> (raw)
In-Reply-To: <20180627144113.6989-1-jani.nikula@intel.com>
On Wed, Jun 27, 2018 at 05:41:13PM +0300, Jani Nikula wrote:
> There's already some BIT() usage here and there, embrace it.
>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 9 +++++----
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 476118f46cf3..64b9c270045d 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -65,9 +65,10 @@
> * but do note that the macros may be needed to read as well as write the
> * register contents.
> *
> - * Define bits using ``(1 << N)`` instead of ``BIT(N)``. We may change this in
> - * the future, but this is the prevailing style. Do **not** add ``_BIT`` suffix
> - * to the name.
> + * Define bits using ``BIT(N)`` instead of ``(1 << N)``. Do **not** add ``_BIT``
> + * suffix to the name. Exception to ``BIT()`` usage: Value 1 for a bit field
> + * should be defined using ``(1 << N)`` to be in line with other values such as
> + * ``(2 << N)`` for the same field.
> *
> * Group the register and its contents together without blank lines, separate
> * from other registers and their contents with one blank line.
> @@ -105,7 +106,7 @@
> * #define _FOO_A 0xf000
> * #define _FOO_B 0xf001
> * #define FOO(pipe) _MMIO_PIPE(pipe, _FOO_A, _FOO_B)
> - * #define FOO_ENABLE (1 << 31)
> + * #define FOO_ENABLE BIT(31)
Oh! I'm sure that I will miss the (1 << n) notation...
and right now we had just converted everything to the documented style...
any chance of get a script modifying all at once?
Anyways:
Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> * #define FOO_MODE_MASK (0xf << 16)
> * #define FOO_MODE_SHIFT 16
> * #define FOO_MODE_BAR (0 << 16)
> --
> 2.11.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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prev parent reply other threads:[~2018-06-28 4:57 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-06-27 14:41 [PATCH] drm/i915: encourage BIT() macro usage in register definitions Jani Nikula
2018-06-27 15:51 ` Michal Wajdeczko
2018-06-27 15:59 ` Chris Wilson
2018-06-28 12:03 ` Jani Nikula
2018-06-28 17:45 ` Paulo Zanoni
2018-06-28 19:05 ` Rodrigo Vivi
2018-06-27 17:25 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-06-27 20:07 ` ✓ Fi.CI.IGT: " Patchwork
2018-06-28 4:57 ` Rodrigo Vivi [this message]
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