All of lore.kernel.org
 help / color / mirror / Atom feed
From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/i915/selftests: Replace magic 1<<22 with MI_USE_GGTT/MI_MEM_VIRTUAL
Date: Fri, 6 Jul 2018 17:47:25 +0300	[thread overview]
Message-ID: <20180706144725.GL5565@intel.com> (raw)
In-Reply-To: <20180706142323.25699-1-chris@chris-wilson.co.uk>

On Fri, Jul 06, 2018 at 03:23:22PM +0100, Chris Wilson wrote:
> Replace the magic bit with the proper symbolic name for instructing
> MI_STORE_DWORD_IMM to use a virtual address (on gen3) or the global GTT
> address (still virtual!) on gen4+.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  drivers/gpu/drm/i915/selftests/huge_pages.c         | 4 ++--
>  drivers/gpu/drm/i915/selftests/i915_gem_coherency.c | 4 ++--
>  drivers/gpu/drm/i915/selftests/i915_gem_context.c   | 4 ++--
>  drivers/gpu/drm/i915/selftests/intel_hangcheck.c    | 2 +-
>  4 files changed, 7 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/selftests/huge_pages.c b/drivers/gpu/drm/i915/selftests/huge_pages.c
> index 1193dd36913a..ab662dabcff7 100644
> --- a/drivers/gpu/drm/i915/selftests/huge_pages.c
> +++ b/drivers/gpu/drm/i915/selftests/huge_pages.c
> @@ -919,12 +919,12 @@ gpu_write_dw(struct i915_vma *vma, u64 offset, u32 val)
>  			*cmd++ = val;
>  		} else if (gen >= 4) {
>  			*cmd++ = MI_STORE_DWORD_IMM_GEN4 |
> -				(gen < 6 ? 1 << 22 : 0);
> +				(gen < 6 ? MI_USE_GGTT : 0);
>  			*cmd++ = 0;
>  			*cmd++ = offset;
>  			*cmd++ = val;
>  		} else {
> -			*cmd++ = MI_STORE_DWORD_IMM | 1 << 22;
> +			*cmd++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
>  			*cmd++ = offset;
>  			*cmd++ = val;
>  		}
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
> index cb9eef1635e1..294c58aba2c1 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_coherency.c
> @@ -210,12 +210,12 @@ static int gpu_set(struct drm_i915_gem_object *obj,
>  		*cs++ = upper_32_bits(i915_ggtt_offset(vma) + offset);
>  		*cs++ = v;

Missed the gen8+ case here?

>  	} else if (INTEL_GEN(i915) >= 4) {
> -		*cs++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22;
> +		*cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;

So here we use ggtt on all gens. In the other tests we use ppgtt on
gen6+. Ah, this one uses the kernel context apparently. I guess that's
the reason?

>  		*cs++ = 0;
>  		*cs++ = i915_ggtt_offset(vma) + offset;
>  		*cs++ = v;
>  	} else {
> -		*cs++ = MI_STORE_DWORD_IMM | 1 << 22;
> +		*cs++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
>  		*cs++ = i915_ggtt_offset(vma) + offset;
>  		*cs++ = v;
>  		*cs++ = MI_NOOP;
> diff --git a/drivers/gpu/drm/i915/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> index 0d8e719802fa..65100d3e31cf 100644
> --- a/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/selftests/i915_gem_context.c
> @@ -63,12 +63,12 @@ gpu_fill_dw(struct i915_vma *vma, u64 offset, unsigned long count, u32 value)
>  			*cmd++ = value;
>  		} else if (gen >= 4) {
>  			*cmd++ = MI_STORE_DWORD_IMM_GEN4 |
> -				(gen < 6 ? 1 << 22 : 0);
> +				(gen < 6 ? MI_USE_GGTT : 0);
>  			*cmd++ = 0;
>  			*cmd++ = offset;
>  			*cmd++ = value;
>  		} else {
> -			*cmd++ = MI_STORE_DWORD_IMM | 1 << 22;
> +			*cmd++ = MI_STORE_DWORD_IMM | MI_MEM_VIRTUAL;
>  			*cmd++ = offset;
>  			*cmd++ = value;
>  		}
> diff --git a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> index 5cb808dc5b50..0fc6da81f86e 100644
> --- a/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> +++ b/drivers/gpu/drm/i915/selftests/intel_hangcheck.c
> @@ -171,7 +171,7 @@ static int emit_recurse_batch(struct hang *h,
>  		*batch++ = MI_BATCH_BUFFER_START | 1 << 8;
>  		*batch++ = lower_32_bits(vma->node.start);
>  	} else if (INTEL_GEN(i915) >= 4) {
> -		*batch++ = MI_STORE_DWORD_IMM_GEN4 | 1 << 22;
> +		*batch++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
>  		*batch++ = 0;
>  		*batch++ = lower_32_bits(hws_address(hws, rq));
>  		*batch++ = rq->fence.seqno;
> -- 
> 2.18.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  parent reply	other threads:[~2018-07-06 14:47 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-06 14:23 [PATCH 1/2] drm/i915/selftests: Replace magic 1<<22 with MI_USE_GGTT/MI_MEM_VIRTUAL Chris Wilson
2018-07-06 14:23 ` [PATCH 2/2] drm/i915/selftests: Fixup missing MI_MEM_VIRTUAL for live_hangcheck Chris Wilson
2018-07-06 14:47   ` Ville Syrjälä
2018-07-06 14:47 ` Ville Syrjälä [this message]
2018-07-06 14:53   ` [PATCH 1/2] drm/i915/selftests: Replace magic 1<<22 with MI_USE_GGTT/MI_MEM_VIRTUAL Chris Wilson
2018-07-06 16:03 ` ✓ Fi.CI.BAT: success for series starting with [1/2] " Patchwork
2018-07-07 13:17 ` ✗ Fi.CI.IGT: failure " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20180706144725.GL5565@intel.com \
    --to=ville.syrjala@linux.intel.com \
    --cc=chris@chris-wilson.co.uk \
    --cc=intel-gfx@lists.freedesktop.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.