Re: [PATCH] drm/dp: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

[Manasi Navare <manasi.d.navare@intel.com>]

Matt, is the new revision already submitted to the M-L?

Manasi

On Tue, Jun 26, 2018 at 07:54:19AM -0700, Atwood, Matthew S wrote:
> ill uprev by EOD
> ________________________________________
> From: Navare, Manasi D
> Sent: Monday, June 25, 2018 5:39 PM
> To: Atwood, Matthew S
> Cc: intel-gfx@lists.freedesktop.org; Vivi, Rodrigo; bleung@chromium.org; Zanoni, Paulo R
> Subject: Re: [Intel-gfx] [PATCH] drm/dp: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT
> 
> What is the status of this patch?
> I am hitting this issue with one of the DP 1.4 sinks where the correct
> values of DPCD are present at this new offset of 0x2200 else I see
> bad values for REV and Max_link_rate etc..
> So we absolutely need this for DP 1.4 sinks.
> 
> Manasi
> 
> On Wed, May 16, 2018 at 09:33:42AM -0700, matthew.s.atwood@intel.com wrote:
> > From: Matt Atwood <matthew.s.atwood@intel.com>
> >
> > According to DP spec (2.9.3.1 of DP 1.4) if
> > EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD
> > 02200h through 0220Fh shall contain the DPRX's true capability. These
> > values will match 00000h through 0000Fh, except for DPCD_REV,
> > MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.
> >
> > Read from DPCD once for all 3 values as this is an expensive operation.
> > Spec mentions that all of address space 02200h through 0220Fh should
> > contain the right information however currently only 3 values can
> > differ.
> >
> > There is no address space in the intel_dp->dpcd struct for addresses
> > 02200h through 0220Fh, and since so much of the data is a identical,
> > simply overwrite the values stored in 00000h through 0000Fh with the
> > values that can be overwritten from addresses 02200h through 0220Fh
> >
> > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 14 ++++++++++++++
> >  include/drm/drm_dp_helper.h     |  5 +++--
> >  2 files changed, 17 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> > index dde92e4af5d3..899ebc5cece6 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -3738,6 +3738,20 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp)
> >                            sizeof(intel_dp->dpcd)) < 0)
> >               return false; /* aux transfer failed */
> >
> > +     if (intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
> > +         DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT &&
> > +         intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) {
> > +             uint8_t dpcd_ext[16];
> > +
> > +             if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
> > +                 &dpcd_ext, sizeof(dpcd_ext)) < 0)
> > +                     return false; /* aux transfer failed */
> > +
> > +             intel_dp->dpcd[DP_DPCD_REV] = dpcd_ext[DP_DPCD_REV];
> > +             intel_dp->dpcd[DP_MAX_LINK_RATE] = dpcd_ext[DP_MAX_LINK_RATE];
> > +             intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] =
> > +                     dpcd_ext[DP_DOWNSTREAMPORT_PRESENT];
> > +     }
> >       DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
> >
> >       return intel_dp->dpcd[DP_DPCD_REV] != 0;
> > diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> > index c01564991a9f..757bd5913f3d 100644
> > --- a/include/drm/drm_dp_helper.h
> > +++ b/include/drm/drm_dp_helper.h
> > @@ -123,8 +123,9 @@
> >  # define DP_FRAMING_CHANGE_CAP                   (1 << 1)
> >  # define DP_DPCD_DISPLAY_CONTROL_CAPABLE     (1 << 3) /* edp v1.2 or higher */
> >
> > -#define DP_TRAINING_AUX_RD_INTERVAL         0x00e   /* XXX 1.2? */
> > -# define DP_TRAINING_AUX_RD_MASK            0x7F    /* XXX 1.2? */
> > +#define DP_TRAINING_AUX_RD_INTERVAL             0x00e   /* XXX 1.2? */
> > +# define DP_TRAINING_AUX_RD_MASK                0x7F    /* XXX 1.2? */
> > +# define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7)/* XXX 1.2? */
> >
> >  #define DP_ADAPTER_CAP                           0x00f   /* 1.2 */
> >  # define DP_FORCE_LOAD_SENSE_CAP         (1 << 0)
> > --
> > 2.17.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
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