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From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
To: speck@linutronix.de
Subject: [MODERATED] Re: [PATCH v9] Command-line
Date: Wed, 11 Jul 2018 13:42:52 -0400	[thread overview]
Message-ID: <20180711174252.GC5485@char.us.oracle.com> (raw)
In-Reply-To: <nycvar.YFH.7.76.1807110142070.997@cbobk.fhfr.pm>

> @@ -1989,6 +1983,45 @@
>  			feature (tagged TLBs) on capable Intel chips.
>  			Default is 1 (enabled)
>  
> +	l1tf=           [X86] Control mitigation of the L1TF vulnerability on
> +			      affected CPUs
> +
> +			The kernel PTE inversion protection is unconditionally
> +			enabled and cannot be disabled.
> +
> +			full
> +				Provides all available mitigations for the L1TF
> +				vulnerability. Disables SMT and enable all
> +				mitigations in the hypervisors. SMT control via
> +				/sys/devices/system/cpu/smt/control is still
> +				possible after boot. Hypervisors will issue a
> +				warning when the first VM is started in a
> +				pontetially insecure configuration, i.e. SMT

s/pontetially/potentially/

      parent reply	other threads:[~2018-07-11 17:43 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-11  0:00 [MODERATED] [PATCH v9] Command-line Jiri Kosina
2018-07-11  5:29 ` [MODERATED] " Josh Poimboeuf
2018-07-11 17:42 ` Konrad Rzeszutek Wilk [this message]

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