diff for duplicates of <20180713172626.5ca0e30f@xhacker.debian> diff --git a/a/1.txt b/N1/1.txt index 7bdb80b..b4c0812 100644 --- a/a/1.txt +++ b/N1/1.txt @@ -41,7 +41,7 @@ index 000000000000..20f3d658c566 + #address-cells = <1>; + #size-cells = <0>; + -+ cpu0: cpu at 0 { ++ cpu0: cpu@0 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x0>; @@ -50,7 +50,7 @@ index 000000000000..20f3d658c566 + cpu-idle-states = <&CPU_SLEEP_0>; + }; + -+ cpu1: cpu at 1 { ++ cpu1: cpu@1 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x1>; @@ -59,7 +59,7 @@ index 000000000000..20f3d658c566 + cpu-idle-states = <&CPU_SLEEP_0>; + }; + -+ cpu2: cpu at 2 { ++ cpu2: cpu@2 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x2>; @@ -68,7 +68,7 @@ index 000000000000..20f3d658c566 + cpu-idle-states = <&CPU_SLEEP_0>; + }; + -+ cpu3: cpu at 3 { ++ cpu3: cpu@3 { + compatible = "arm,cortex-a53", "arm,armv8"; + device_type = "cpu"; + reg = <0x3>; @@ -120,13 +120,13 @@ index 000000000000..20f3d658c566 + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + -+ soc at f7000000 { ++ soc@f7000000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xf7000000 0x1000000>; + -+ gic: interrupt-controller at 901000 { ++ gic: interrupt-controller@901000 { + compatible = "arm,gic-400"; + #interrupt-cells = <3>; + interrupt-controller; @@ -137,13 +137,13 @@ index 000000000000..20f3d658c566 + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; + }; + -+ apb at e80000 { ++ apb@e80000 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0xe80000 0x10000>; + -+ uart0: uart at 0c00 { ++ uart0: uart@0c00 { + compatible = "snps,dw-apb-uart"; + reg = <0x0c00 0x100>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; @@ -152,13 +152,13 @@ index 000000000000..20f3d658c566 + status = "disabled"; + }; + -+ gpio0: gpio at 1800 { ++ gpio0: gpio@1800 { + compatible = "snps,dw-apb-gpio"; + reg = <0x1800 0x400>; + #address-cells = <1>; + #size-cells = <0>; + -+ porta: gpio-port at 0 { ++ porta: gpio-port@0 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; @@ -170,13 +170,13 @@ index 000000000000..20f3d658c566 + }; + }; + -+ gpio1: gpio at 2000 { ++ gpio1: gpio@2000 { + compatible = "snps,dw-apb-gpio"; + reg = <0x2000 0x400>; + #address-cells = <1>; + #size-cells = <0>; + -+ portb: gpio-port at 1 { ++ portb: gpio-port@1 { + compatible = "snps,dw-apb-gpio-port"; + gpio-controller; + #gpio-cells = <2>; diff --git a/a/content_digest b/N1/content_digest index 245dd9e..1d141a2 100644 --- a/a/content_digest +++ b/N1/content_digest @@ -1,8 +1,13 @@ "ref\020180713171712.05f58a74@xhacker.debian\0" - "From\0Jisheng.Zhang@synaptics.com (Jisheng Zhang)\0" + "From\0Jisheng Zhang <Jisheng.Zhang@synaptics.com>\0" "Subject\0[PATCH 3/3] arm64: dts: synaptics: add dtsi file for Synaptics AS370 SoC\0" "Date\0Fri, 13 Jul 2018 17:26:26 +0800\0" - "To\0linux-arm-kernel@lists.infradead.org\0" + "To\0Rob Herring <robh+dt@kernel.org>" + " Mark Rutland <mark.rutland@arm.com>\0" + "Cc\0devicetree@vger.kernel.org" + linux-kernel@vger.kernel.org + linux-arm-kernel@lists.infradead.org + " Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>\0" "\00:1\0" "b\0" "Add initial dtsi file to support Synaptics AS370 SoC with quad\n" @@ -48,7 +53,7 @@ "+\t\t#address-cells = <1>;\n" "+\t\t#size-cells = <0>;\n" "+\n" - "+\t\tcpu0: cpu at 0 {\n" + "+\t\tcpu0: cpu@0 {\n" "+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\treg = <0x0>;\n" @@ -57,7 +62,7 @@ "+\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n" "+\t\t};\n" "+\n" - "+\t\tcpu1: cpu at 1 {\n" + "+\t\tcpu1: cpu@1 {\n" "+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\treg = <0x1>;\n" @@ -66,7 +71,7 @@ "+\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n" "+\t\t};\n" "+\n" - "+\t\tcpu2: cpu at 2 {\n" + "+\t\tcpu2: cpu@2 {\n" "+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\treg = <0x2>;\n" @@ -75,7 +80,7 @@ "+\t\t\tcpu-idle-states = <&CPU_SLEEP_0>;\n" "+\t\t};\n" "+\n" - "+\t\tcpu3: cpu at 3 {\n" + "+\t\tcpu3: cpu@3 {\n" "+\t\t\tcompatible = \"arm,cortex-a53\", \"arm,armv8\";\n" "+\t\t\tdevice_type = \"cpu\";\n" "+\t\t\treg = <0x3>;\n" @@ -127,13 +132,13 @@ "+\t\t\t <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;\n" "+\t};\n" "+\n" - "+\tsoc at f7000000 {\n" + "+\tsoc@f7000000 {\n" "+\t\tcompatible = \"simple-bus\";\n" "+\t\t#address-cells = <1>;\n" "+\t\t#size-cells = <1>;\n" "+\t\tranges = <0 0 0xf7000000 0x1000000>;\n" "+\n" - "+\t\tgic: interrupt-controller at 901000 {\n" + "+\t\tgic: interrupt-controller@901000 {\n" "+\t\t\tcompatible = \"arm,gic-400\";\n" "+\t\t\t#interrupt-cells = <3>;\n" "+\t\t\tinterrupt-controller;\n" @@ -144,13 +149,13 @@ "+\t\t\tinterrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;\n" "+\t\t};\n" "+\n" - "+\t\tapb at e80000 {\n" + "+\t\tapb@e80000 {\n" "+\t\t\tcompatible = \"simple-bus\";\n" "+\t\t\t#address-cells = <1>;\n" "+\t\t\t#size-cells = <1>;\n" "+\t\t\tranges = <0 0xe80000 0x10000>;\n" "+\n" - "+\t\t\tuart0: uart at 0c00 {\n" + "+\t\t\tuart0: uart@0c00 {\n" "+\t\t\t\tcompatible = \"snps,dw-apb-uart\";\n" "+\t\t\t\treg = <0x0c00 0x100>;\n" "+\t\t\t\tinterrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;\n" @@ -159,13 +164,13 @@ "+\t\t\t\tstatus = \"disabled\";\n" "+\t\t\t};\n" "+\n" - "+\t\t\tgpio0: gpio at 1800 {\n" + "+\t\t\tgpio0: gpio@1800 {\n" "+\t\t\t\tcompatible = \"snps,dw-apb-gpio\";\n" "+\t\t\t\treg = <0x1800 0x400>;\n" "+\t\t\t\t#address-cells = <1>;\n" "+\t\t\t\t#size-cells = <0>;\n" "+\n" - "+\t\t\t\tporta: gpio-port at 0 {\n" + "+\t\t\t\tporta: gpio-port@0 {\n" "+\t\t\t\t\tcompatible = \"snps,dw-apb-gpio-port\";\n" "+\t\t\t\t\tgpio-controller;\n" "+\t\t\t\t\t#gpio-cells = <2>;\n" @@ -177,13 +182,13 @@ "+\t\t\t\t};\n" "+\t\t\t};\n" "+\n" - "+\t\t\tgpio1: gpio at 2000 {\n" + "+\t\t\tgpio1: gpio@2000 {\n" "+\t\t\t\tcompatible = \"snps,dw-apb-gpio\";\n" "+\t\t\t\treg = <0x2000 0x400>;\n" "+\t\t\t\t#address-cells = <1>;\n" "+\t\t\t\t#size-cells = <0>;\n" "+\n" - "+\t\t\t\tportb: gpio-port at 1 {\n" + "+\t\t\t\tportb: gpio-port@1 {\n" "+\t\t\t\t\tcompatible = \"snps,dw-apb-gpio-port\";\n" "+\t\t\t\t\tgpio-controller;\n" "+\t\t\t\t\t#gpio-cells = <2>;\n" @@ -200,4 +205,4 @@ "-- \n" 2.18.0 -3ade934c3214abda3eb7d22762a2f76419e49a05c90a15c0d9a6b052a335f9cd +502e2f72dee16e3b1730744e238e68db7ae30ac98f776c6a28fae436b5db3e4a
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