All of lore.kernel.org
 help / color / mirror / Atom feed
From: Ingo Molnar <mingo@kernel.org>
To: Masayoshi Mizuma <msys.mizuma@gmail.com>,
	Kan Liang <kan.liang@intel.com>
Cc: Thomas Gleixner <tglx@linutronix.de>,
	Ingo Molnar <mingo@redhat.com>, "H. Peter Anvin" <hpa@zytor.com>,
	x86@kernel.org, linux-kernel@vger.kernel.org,
	Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
Subject: Re: [PATCH] [RESEND] perf/x86/intel/uncore: Fix the index of PCU.3 Broadwell CPUs
Date: Mon, 16 Jul 2018 00:34:44 +0200	[thread overview]
Message-ID: <20180715223444.GA16209@gmail.com> (raw)
In-Reply-To: <20180710233158.21037-1-msys.mizuma@gmail.com>


* Masayoshi Mizuma <msys.mizuma@gmail.com> wrote:

> From: Masayoshi Mizuma <m.mizuma@jp.fujitsu.com>
> 
> commit 15a3e845b01c ("perf/x86/intel/uncore: Fix SBOX support for
> Broadwell CPUs") introduced PCU.3 for Broadwell CPU. Unfortunately,
> the driver_data of PCU.3 conflicts to QPI Port 2 filter.
> 
>     { /* QPI Port 2 filter  */
>             PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6f46),
>             .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV, 2),
> 
>     { /* PCU.3 (for Capability registers) */
>             PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x6fc0),
>             .driver_data = UNCORE_PCI_DEV_DATA(UNCORE_EXTRA_PCI_DEV,
>                                                HSWEP_PCI_PCU_3),
>                              // HSWEP_PCI_PCU_3 == 2

> --- a/arch/x86/events/intel/uncore_snbep.c
> +++ b/arch/x86/events/intel/uncore_snbep.c
> @@ -1030,6 +1030,7 @@ enum {
>  	SNBEP_PCI_QPI_PORT0_FILTER,
>  	SNBEP_PCI_QPI_PORT1_FILTER,
>  	HSWEP_PCI_PCU_3,
> +	BDX_PCI_PCU_3,
>  };

So we use a magic '2' enumerator in the 'QPI Port 2 filter', and that overlaps 
with HSWEP_PCI_PCU_3, right?

Shouldn't we clean up all the enumerators and not use magic numbers, and this fix 
the conflict?

Thanks,

	Ingo

  reply	other threads:[~2018-07-15 22:36 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-10 23:31 [PATCH] [RESEND] perf/x86/intel/uncore: Fix the index of PCU.3 Broadwell CPUs Masayoshi Mizuma
2018-07-15 22:34 ` Ingo Molnar [this message]
2018-07-16 14:29   ` Liang, Kan
2018-07-16 15:07     ` Masayoshi Mizuma
2018-07-16 16:31       ` Liang, Kan
2018-07-17 16:37         ` Masayoshi Mizuma
2018-07-27 17:00           ` Masayoshi Mizuma
2018-07-30 10:06             ` Ingo Molnar
2018-07-30 12:13               ` Liang, Kan

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20180715223444.GA16209@gmail.com \
    --to=mingo@kernel.org \
    --cc=hpa@zytor.com \
    --cc=kan.liang@intel.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=m.mizuma@jp.fujitsu.com \
    --cc=mingo@redhat.com \
    --cc=msys.mizuma@gmail.com \
    --cc=tglx@linutronix.de \
    --cc=x86@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.