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[211.20.114.70]) by smtp.gmail.com with ESMTPSA id n86-v6sm303876pfj.68.2018.07.16.23.05.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Jul 2018 23:05:59 -0700 (PDT) Date: Tue, 17 Jul 2018 14:04:11 +0800 From: Ryan Chen To: Benjamin Herrenschmidt Cc: openbmc@lists.ozlabs.org, joel@jms.id.au, andrew@aj.id.au, ryan_chen@aspeedtech.com, mine260309@gmail.com Subject: Re: [PATCH linux dev-4.17 1/7] clk: Aspeed: Modify clk-aspeed.c driver probe sequence Message-ID: <20180717060411.GA10750@ryan-ubuntu> References: <1531286230-28453-1-git-send-email-ryanchen.aspeed@gmail.com> <1531286230-28453-2-git-send-email-ryanchen.aspeed@gmail.com> <84064771141b017e5fe3cafef8dc8307f5d97eba.camel@kernel.crashing.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <84064771141b017e5fe3cafef8dc8307f5d97eba.camel@kernel.crashing.org> User-Agent: Mutt/1.5.24 (2015-08-30) X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 17 Jul 2018 06:06:05 -0000 On Wed, Jul 11, 2018 at 03:47:56PM +1000, Benjamin Herrenschmidt wrote: > On Wed, 2018-07-11 at 13:17 +0800, Ryan Chen wrote: > > In Aspeed's SoC, all IP clk gating and pll parameter is in scu > > controller, before IP driver probe, scu driver need prepare for it. > > So buildin_platform_driver to core_initcall. > > > > Signed-off-by: Ryan Chen > > --- > > drivers/clk/clk-aspeed.c | 7 ++++++- > > 1 file changed, 6 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/clk/clk-aspeed.c b/drivers/clk/clk-aspeed.c > > index 8796b8a..9e55743 100644 > > --- a/drivers/clk/clk-aspeed.c > > +++ b/drivers/clk/clk-aspeed.c > > @@ -573,7 +573,12 @@ static struct platform_driver aspeed_clk_driver = { > > .suppress_bind_attrs = true, > > }, > > }; > > -builtin_platform_driver(aspeed_clk_driver); > > + > > +static int __init aspeed_clk_init(void) > > +{ > > + return platform_driver_register(&aspeed_clk_driver); > > +} > > +core_initcall(aspeed_clk_init); > > > > static void __init aspeed_ast2400_cc(struct regmap *map) > > { > > It's generally considered dangerous to register drivers at core > initcall time. Understand. But if interrupt controller have clk gating. the scu driver should be eraly than irq chip driver probe. Is this point is reasonable? > > Any reason we don't use the generic clock driver registration mechanism > that runs at of_clk_init() time ? I will use "if (gate->reset_idx == aspeed_resets[ASPEED_RESET_SDHCI])", is it suitable ? Ryan Chen > > Cheers, > Ben. >