From mboxrd@z Thu Jan  1 00:00:00 1970
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: Re: [PATCH] drm/i915: Flush chipset caches after GGTT
 writes
Date: Tue, 17 Jul 2018 07:32:08 -0700
Message-ID: <20180717143208.GB7043@intel.com>
References: <20180717092655.28417-1-chris@chris-wilson.co.uk>
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