From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 4/5] drm/omapdrm: Substitute format_is_yuv() with format->is_yuv Date: Wed, 18 Jul 2018 13:17:41 +0300 Message-ID: <20180718101741.GU5565@intel.com> References: <1531847626-22248-1-git-send-email-ayan.halder@arm.com> <1531847626-22248-4-git-send-email-ayan.halder@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Content-Disposition: inline In-Reply-To: <1531847626-22248-4-git-send-email-ayan.halder@arm.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" To: Ayan Kumar Halder Cc: heiko@sntech.de, airlied@linux.ie, dri-devel@lists.freedesktop.org, hjc@rock-chips.com, peter.ujfalusi@ti.com, laurent.pinchart@ideasonboard.com, afd@ti.com, maxime.ripard@bootlin.com, linux-rockchip@lists.infradead.org, wens@csie.org, tomi.valkeinen@ti.com, malidp@foss.arm.com, intel-gfx@lists.freedesktop.org, bparrot@ti.com, rodrigo.vivi@intel.com, nd@arm.com, linux-arm-kernel@lists.infradead.org, sre@kernel.org, linux-kernel@vger.kernel.org List-Id: linux-rockchip.vger.kernel.org T24gVHVlLCBKdWwgMTcsIDIwMTggYXQgMDY6MTM6NDVQTSArMDEwMCwgQXlhbiBLdW1hciBIYWxk ZXIgd3JvdGU6Cj4gZHJtX2Zvcm1hdF9pbmZvIHRhYmxlIGhhcyBhIGZpZWxkICdpc195dXYnIHRv IGRlbm90ZSBpZiB0aGUgZm9ybWF0Cj4gaXMgeXV2IG9yIG5vdC4gVGhlIGRyaXZlciBpcyBleHBl Y3RlZCB0byB1c2UgdGhpcyBpbnN0ZWFkIG9mCj4gaGF2aW5nIGEgZnVuY3Rpb24gZm9yIHRoZSBz YW1lIHB1cnBvc2UuCj4gCj4gU2lnbmVkLW9mZi1ieTogQXlhbiBLdW1hciBoYWxkZXIgPGF5YW4u aGFsZGVyQGFybS5jb20+Cj4gLS0tCj4gIGRyaXZlcnMvZ3B1L2RybS9vbWFwZHJtL2Rzcy9kaXNw Yy5jIHwgMjYgKysrKysrKysrKy0tLS0tLS0tLS0tLS0tLS0KPiAgMSBmaWxlIGNoYW5nZWQsIDEw IGluc2VydGlvbnMoKyksIDE2IGRlbGV0aW9ucygtKQo+IAo+IGRpZmYgLS1naXQgYS9kcml2ZXJz L2dwdS9kcm0vb21hcGRybS9kc3MvZGlzcGMuYyBiL2RyaXZlcnMvZ3B1L2RybS9vbWFwZHJtL2Rz cy9kaXNwYy5jCj4gaW5kZXggODRmMjc0Yy4uOGQyZDdhNCAxMDA2NDQKPiAtLS0gYS9kcml2ZXJz L2dwdS9kcm0vb21hcGRybS9kc3MvZGlzcGMuYwo+ICsrKyBiL2RyaXZlcnMvZ3B1L2RybS9vbWFw ZHJtL2Rzcy9kaXNwYy5jCj4gQEAgLTExNDAsMTggKzExNDAsNiBAQCBzdGF0aWMgdm9pZCBkaXNw Y19vdmxfc2V0X2NvbG9yX21vZGUoc3RydWN0IGRpc3BjX2RldmljZSAqZGlzcGMsCj4gIAlSRUdf RkxEX01PRChkaXNwYywgRElTUENfT1ZMX0FUVFJJQlVURVMocGxhbmUpLCBtLCA0LCAxKTsKPiAg fQo+ICAKPiAtc3RhdGljIGJvb2wgZm9ybWF0X2lzX3l1dih1MzIgZm91cmNjKQo+IC17Cj4gLQlz d2l0Y2ggKGZvdXJjYykgewo+IC0JY2FzZSBEUk1fRk9STUFUX1lVWVY6Cj4gLQljYXNlIERSTV9G T1JNQVRfVVlWWToKPiAtCWNhc2UgRFJNX0ZPUk1BVF9OVjEyOgo+IC0JCXJldHVybiB0cnVlOwo+ IC0JZGVmYXVsdDoKPiAtCQlyZXR1cm4gZmFsc2U7Cj4gLQl9Cj4gLX0KPiAtCj4gIHN0YXRpYyB2 b2lkIGRpc3BjX292bF9jb25maWd1cmVfYnVyc3RfdHlwZShzdHJ1Y3QgZGlzcGNfZGV2aWNlICpk aXNwYywKPiAgCQkJCQkgICBlbnVtIG9tYXBfcGxhbmVfaWQgcGxhbmUsCj4gIAkJCQkJICAgZW51 bSBvbWFwX2Rzc19yb3RhdGlvbl90eXBlIHJvdGF0aW9uKQo+IEBAIC0xOTEwLDExICsxODk4LDE0 IEBAIHN0YXRpYyB2b2lkIGRpc3BjX292bF9zZXRfc2NhbGluZ191dihzdHJ1Y3QgZGlzcGNfZGV2 aWNlICpkaXNwYywKPiAgCWludCBzY2FsZV94ID0gb3V0X3dpZHRoICE9IG9yaWdfd2lkdGg7Cj4g IAlpbnQgc2NhbGVfeSA9IG91dF9oZWlnaHQgIT0gb3JpZ19oZWlnaHQ7Cj4gIAlib29sIGNocm9t YV91cHNjYWxlID0gcGxhbmUgIT0gT01BUF9EU1NfV0I7Cj4gKwljb25zdCBzdHJ1Y3QgZHJtX2Zv cm1hdF9pbmZvICppbmZvOwo+ICsKPiArCWluZm8gPSBkcm1fZm9ybWF0X2luZm8oZm91cmNjKTsK Ck5vdCBzdXJlIFRvbWkgd2FudHMgZHJtIHVzYWdlIChhcGFydCBmcm9tIHRoZSBmb3VyY2NzKSBp bnNpZGUgdGhlCmRzcyBjb2RlLgoKPiAgCj4gIAlpZiAoIWRpc3BjX2hhc19mZWF0dXJlKGRpc3Bj LCBGRUFUX0hBTkRMRV9VVl9TRVBBUkFURSkpCj4gIAkJcmV0dXJuOwo+ICAKPiAtCWlmICghZm9y bWF0X2lzX3l1dihmb3VyY2MpKSB7Cj4gKwlpZiAoIWluZm8tPmlzX3l1dikgewo+ICAJCS8qIHJl c2V0IGNocm9tYSByZXNhbXBsaW5nIGZvciBSR0IgZm9ybWF0cyAgKi8KPiAgCQlpZiAocGxhbmUg IT0gT01BUF9EU1NfV0IpCj4gIAkJCVJFR19GTERfTU9EKGRpc3BjLCBESVNQQ19PVkxfQVRUUklC VVRFUzIocGxhbmUpLAo+IEBAIC0yNjMyLDYgKzI2MjMsOSBAQCBzdGF0aWMgaW50IGRpc3BjX292 bF9zZXR1cF9jb21tb24oc3RydWN0IGRpc3BjX2RldmljZSAqZGlzcGMsCj4gIAlib29sIGlsYWNl ID0gISEodm0tPmZsYWdzICYgRElTUExBWV9GTEFHU19JTlRFUkxBQ0VEKTsKPiAgCXVuc2lnbmVk IGxvbmcgcGNsayA9IGRpc3BjX3BsYW5lX3BjbGtfcmF0ZShkaXNwYywgcGxhbmUpOwo+ICAJdW5z aWduZWQgbG9uZyBsY2xrID0gZGlzcGNfcGxhbmVfbGNsa19yYXRlKGRpc3BjLCBwbGFuZSk7Cj4g Kwljb25zdCBzdHJ1Y3QgZHJtX2Zvcm1hdF9pbmZvICppbmZvOwo+ICsKPiArCWluZm8gPSBkcm1f Zm9ybWF0X2luZm8oZm91cmNjKTsKPiAgCj4gIAkvKiB3aGVuIHNldHRpbmcgdXAgV0IsIGRpc3Bj X3BsYW5lX3BjbGtfcmF0ZSgpIHJldHVybnMgMCAqLwo+ICAJaWYgKHBsYW5lID09IE9NQVBfRFNT X1dCKQo+IEBAIC0yNjQwLDcgKzI2MzQsNyBAQCBzdGF0aWMgaW50IGRpc3BjX292bF9zZXR1cF9j b21tb24oc3RydWN0IGRpc3BjX2RldmljZSAqZGlzcGMsCj4gIAlpZiAocGFkZHIgPT0gMCAmJiBy b3RhdGlvbl90eXBlICE9IE9NQVBfRFNTX1JPVF9USUxFUikKPiAgCQlyZXR1cm4gLUVJTlZBTDsK PiAgCj4gLQlpZiAoZm9ybWF0X2lzX3l1dihmb3VyY2MpICYmIChpbl93aWR0aCAmIDEpKSB7Cj4g KwlpZiAoaW5mby0+aXNfeXV2ICYmIChpbl93aWR0aCAmIDEpKSB7Cj4gIAkJRFNTRVJSKCJpbnB1 dCB3aWR0aCAlZCBpcyBub3QgZXZlbiBmb3IgWVVWIGZvcm1hdFxuIiwgaW5fd2lkdGgpOwo+ICAJ CXJldHVybiAtRUlOVkFMOwo+ICAJfQo+IEBAIC0yNjgwLDcgKzI2NzQsNyBAQCBzdGF0aWMgaW50 IGRpc3BjX292bF9zZXR1cF9jb21tb24oc3RydWN0IGRpc3BjX2RldmljZSAqZGlzcGMsCj4gIAkJ RFNTREJHKCJwcmVkZWNpbWF0aW9uICVkIHggJXgsIG5ldyBpbnB1dCBzaXplICVkIHggJWRcbiIs Cj4gIAkJCXhfcHJlZGVjaW0sIHlfcHJlZGVjaW0sIGluX3dpZHRoLCBpbl9oZWlnaHQpOwo+ICAK PiAtCWlmIChmb3JtYXRfaXNfeXV2KGZvdXJjYykgJiYgKGluX3dpZHRoICYgMSkpIHsKPiArCWlm IChpbmZvLT5pc195dXYgJiYgKGluX3dpZHRoICYgMSkpIHsKPiAgCQlEU1NEQkcoInByZWRlY2lt YXRlZCBpbnB1dCB3aWR0aCBpcyBub3QgZXZlbiBmb3IgWVVWIGZvcm1hdFxuIik7Cj4gIAkJRFNT REJHKCJhZGp1c3RpbmcgaW5wdXQgd2lkdGggJWQgLT4gJWRcbiIsCj4gIAkJCWluX3dpZHRoLCBp bl93aWR0aCAmIH4xKTsKPiBAQCAtMjY4OCw3ICsyNjgyLDcgQEAgc3RhdGljIGludCBkaXNwY19v dmxfc2V0dXBfY29tbW9uKHN0cnVjdCBkaXNwY19kZXZpY2UgKmRpc3BjLAo+ICAJCWluX3dpZHRo ICY9IH4xOwo+ICAJfQo+ICAKPiAtCWlmIChmb3JtYXRfaXNfeXV2KGZvdXJjYykpCj4gKwlpZiAo aW5mby0+aXNfeXV2KQo+ICAJCWNjb252ID0gMTsKPiAgCj4gIAlpZiAoaWxhY2UgJiYgIWZpZWxk bW9kZSkgewo+IC0tIAo+IDIuNy40Cj4gCj4gX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX18KPiBJbnRlbC1nZnggbWFpbGluZyBsaXN0Cj4gSW50ZWwtZ2Z4QGxp c3RzLmZyZWVkZXNrdG9wLm9yZwo+IGh0dHBzOi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxt YW4vbGlzdGluZm8vaW50ZWwtZ2Z4CgotLSAKVmlsbGUgU3lyasOkbMOkCkludGVsCl9fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCkludGVsLWdmeCBtYWlsaW5n IGxpc3QKSW50ZWwtZ2Z4QGxpc3RzLmZyZWVkZXNrdG9wLm9yZwpodHRwczovL2xpc3RzLmZyZWVk ZXNrdG9wLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2ludGVsLWdmeAo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: ville.syrjala@linux.intel.com (Ville =?iso-8859-1?Q?Syrj=E4l=E4?=) Date: Wed, 18 Jul 2018 13:17:41 +0300 Subject: [Intel-gfx] [PATCH 4/5] drm/omapdrm: Substitute format_is_yuv() with format->is_yuv In-Reply-To: <1531847626-22248-4-git-send-email-ayan.halder@arm.com> References: <1531847626-22248-1-git-send-email-ayan.halder@arm.com> <1531847626-22248-4-git-send-email-ayan.halder@arm.com> Message-ID: <20180718101741.GU5565@intel.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Tue, Jul 17, 2018 at 06:13:45PM +0100, Ayan Kumar Halder wrote: > drm_format_info table has a field 'is_yuv' to denote if the format > is yuv or not. The driver is expected to use this instead of > having a function for the same purpose. > > Signed-off-by: Ayan Kumar halder > --- > drivers/gpu/drm/omapdrm/dss/dispc.c | 26 ++++++++++---------------- > 1 file changed, 10 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c > index 84f274c..8d2d7a4 100644 > --- a/drivers/gpu/drm/omapdrm/dss/dispc.c > +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c > @@ -1140,18 +1140,6 @@ static void dispc_ovl_set_color_mode(struct dispc_device *dispc, > REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); > } > > -static bool format_is_yuv(u32 fourcc) > -{ > - switch (fourcc) { > - case DRM_FORMAT_YUYV: > - case DRM_FORMAT_UYVY: > - case DRM_FORMAT_NV12: > - return true; > - default: > - return false; > - } > -} > - > static void dispc_ovl_configure_burst_type(struct dispc_device *dispc, > enum omap_plane_id plane, > enum omap_dss_rotation_type rotation) > @@ -1910,11 +1898,14 @@ static void dispc_ovl_set_scaling_uv(struct dispc_device *dispc, > int scale_x = out_width != orig_width; > int scale_y = out_height != orig_height; > bool chroma_upscale = plane != OMAP_DSS_WB; > + const struct drm_format_info *info; > + > + info = drm_format_info(fourcc); Not sure Tomi wants drm usage (apart from the fourccs) inside the dss code. > > if (!dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) > return; > > - if (!format_is_yuv(fourcc)) { > + if (!info->is_yuv) { > /* reset chroma resampling for RGB formats */ > if (plane != OMAP_DSS_WB) > REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), > @@ -2632,6 +2623,9 @@ static int dispc_ovl_setup_common(struct dispc_device *dispc, > bool ilace = !!(vm->flags & DISPLAY_FLAGS_INTERLACED); > unsigned long pclk = dispc_plane_pclk_rate(dispc, plane); > unsigned long lclk = dispc_plane_lclk_rate(dispc, plane); > + const struct drm_format_info *info; > + > + info = drm_format_info(fourcc); > > /* when setting up WB, dispc_plane_pclk_rate() returns 0 */ > if (plane == OMAP_DSS_WB) > @@ -2640,7 +2634,7 @@ static int dispc_ovl_setup_common(struct dispc_device *dispc, > if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER) > return -EINVAL; > > - if (format_is_yuv(fourcc) && (in_width & 1)) { > + if (info->is_yuv && (in_width & 1)) { > DSSERR("input width %d is not even for YUV format\n", in_width); > return -EINVAL; > } > @@ -2680,7 +2674,7 @@ static int dispc_ovl_setup_common(struct dispc_device *dispc, > DSSDBG("predecimation %d x %x, new input size %d x %d\n", > x_predecim, y_predecim, in_width, in_height); > > - if (format_is_yuv(fourcc) && (in_width & 1)) { > + if (info->is_yuv && (in_width & 1)) { > DSSDBG("predecimated input width is not even for YUV format\n"); > DSSDBG("adjusting input width %d -> %d\n", > in_width, in_width & ~1); > @@ -2688,7 +2682,7 @@ static int dispc_ovl_setup_common(struct dispc_device *dispc, > in_width &= ~1; > } > > - if (format_is_yuv(fourcc)) > + if (info->is_yuv) > cconv = 1; > > if (ilace && !fieldmode) { > -- > 2.7.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx at lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrj?l? Intel From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.2 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED,USER_AGENT_MUTT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82FA3ECDFAA for ; Wed, 18 Jul 2018 10:17:52 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 395E72084E for ; Wed, 18 Jul 2018 10:17:52 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 395E72084E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linux.intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728565AbeGRKzB (ORCPT ); Wed, 18 Jul 2018 06:55:01 -0400 Received: from mga03.intel.com ([134.134.136.65]:25358 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726142AbeGRKzB (ORCPT ); Wed, 18 Jul 2018 06:55:01 -0400 X-Amp-Result: UNSCANNABLE X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Jul 2018 03:17:49 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,369,1526367600"; d="scan'208";a="57800717" Received: from stinkbox.fi.intel.com (HELO stinkbox) ([10.237.72.174]) by orsmga008.jf.intel.com with SMTP; 18 Jul 2018 03:17:42 -0700 Received: by stinkbox (sSMTP sendmail emulation); Wed, 18 Jul 2018 13:17:41 +0300 Date: Wed, 18 Jul 2018 13:17:41 +0300 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Ayan Kumar Halder Cc: liviu.dudau@arm.com, brian.starkey@arm.com, gustavo@padovan.org, maarten.lankhorst@linux.intel.com, seanpaul@chromium.org, airlied@linux.ie, jani.nikula@linux.intel.com, joonas.lahtinen@linux.intel.com, rodrigo.vivi@intel.com, intel-gfx@lists.freedesktop.org, hjc@rock-chips.com, heiko@sntech.de, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, tomi.valkeinen@ti.com, laurent.pinchart@ideasonboard.com, sre@kernel.org, bparrot@ti.com, peter.ujfalusi@ti.com, afd@ti.com, dri-devel@lists.freedesktop.org, maxime.ripard@bootlin.com, wens@csie.org, malidp@foss.arm.com, nd@arm.com Subject: Re: [Intel-gfx] [PATCH 4/5] drm/omapdrm: Substitute format_is_yuv() with format->is_yuv Message-ID: <20180718101741.GU5565@intel.com> References: <1531847626-22248-1-git-send-email-ayan.halder@arm.com> <1531847626-22248-4-git-send-email-ayan.halder@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1531847626-22248-4-git-send-email-ayan.halder@arm.com> User-Agent: Mutt/1.9.4 (2018-02-28) Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Jul 17, 2018 at 06:13:45PM +0100, Ayan Kumar Halder wrote: > drm_format_info table has a field 'is_yuv' to denote if the format > is yuv or not. The driver is expected to use this instead of > having a function for the same purpose. > > Signed-off-by: Ayan Kumar halder > --- > drivers/gpu/drm/omapdrm/dss/dispc.c | 26 ++++++++++---------------- > 1 file changed, 10 insertions(+), 16 deletions(-) > > diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c > index 84f274c..8d2d7a4 100644 > --- a/drivers/gpu/drm/omapdrm/dss/dispc.c > +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c > @@ -1140,18 +1140,6 @@ static void dispc_ovl_set_color_mode(struct dispc_device *dispc, > REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); > } > > -static bool format_is_yuv(u32 fourcc) > -{ > - switch (fourcc) { > - case DRM_FORMAT_YUYV: > - case DRM_FORMAT_UYVY: > - case DRM_FORMAT_NV12: > - return true; > - default: > - return false; > - } > -} > - > static void dispc_ovl_configure_burst_type(struct dispc_device *dispc, > enum omap_plane_id plane, > enum omap_dss_rotation_type rotation) > @@ -1910,11 +1898,14 @@ static void dispc_ovl_set_scaling_uv(struct dispc_device *dispc, > int scale_x = out_width != orig_width; > int scale_y = out_height != orig_height; > bool chroma_upscale = plane != OMAP_DSS_WB; > + const struct drm_format_info *info; > + > + info = drm_format_info(fourcc); Not sure Tomi wants drm usage (apart from the fourccs) inside the dss code. > > if (!dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) > return; > > - if (!format_is_yuv(fourcc)) { > + if (!info->is_yuv) { > /* reset chroma resampling for RGB formats */ > if (plane != OMAP_DSS_WB) > REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), > @@ -2632,6 +2623,9 @@ static int dispc_ovl_setup_common(struct dispc_device *dispc, > bool ilace = !!(vm->flags & DISPLAY_FLAGS_INTERLACED); > unsigned long pclk = dispc_plane_pclk_rate(dispc, plane); > unsigned long lclk = dispc_plane_lclk_rate(dispc, plane); > + const struct drm_format_info *info; > + > + info = drm_format_info(fourcc); > > /* when setting up WB, dispc_plane_pclk_rate() returns 0 */ > if (plane == OMAP_DSS_WB) > @@ -2640,7 +2634,7 @@ static int dispc_ovl_setup_common(struct dispc_device *dispc, > if (paddr == 0 && rotation_type != OMAP_DSS_ROT_TILER) > return -EINVAL; > > - if (format_is_yuv(fourcc) && (in_width & 1)) { > + if (info->is_yuv && (in_width & 1)) { > DSSERR("input width %d is not even for YUV format\n", in_width); > return -EINVAL; > } > @@ -2680,7 +2674,7 @@ static int dispc_ovl_setup_common(struct dispc_device *dispc, > DSSDBG("predecimation %d x %x, new input size %d x %d\n", > x_predecim, y_predecim, in_width, in_height); > > - if (format_is_yuv(fourcc) && (in_width & 1)) { > + if (info->is_yuv && (in_width & 1)) { > DSSDBG("predecimated input width is not even for YUV format\n"); > DSSDBG("adjusting input width %d -> %d\n", > in_width, in_width & ~1); > @@ -2688,7 +2682,7 @@ static int dispc_ovl_setup_common(struct dispc_device *dispc, > in_width &= ~1; > } > > - if (format_is_yuv(fourcc)) > + if (info->is_yuv) > cconv = 1; > > if (ilace && !fieldmode) { > -- > 2.7.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel