All of lore.kernel.org
 help / color / mirror / Atom feed
From: Lukas Wunner <lukas@wunner.de>
To: Mika Westerberg <mika.westerberg@linux.intel.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
	"Rafael J. Wysocki" <rafael.j.wysocki@intel.com>,
	Ashok Raj <ashok.raj@intel.com>,
	Keith Busch <keith.busch@intel.com>,
	Yinghai Lu <yinghai@kernel.org>, Sinan Kaya <okaya@kernel.org>,
	linux-pci@vger.kernel.org,
	Andreas Noever <andreas.noever@gmail.com>
Subject: Re: [PATCH 32/32] PCI: Whitelist Thunderbolt ports for runtime D3
Date: Wed, 18 Jul 2018 21:30:53 +0200	[thread overview]
Message-ID: <20180718193053.GA20124@wunner.de> (raw)
In-Reply-To: <20180621111354.GW2558@lahna.fi.intel.com>

Hi Mika,

sorry for the delay!

On Thu, Jun 21, 2018 at 02:13:54PM +0300, Mika Westerberg wrote:
> On Sat, Jun 16, 2018 at 09:25:00PM +0200, Lukas Wunner wrote:
> > +		/* Even the oldest 2010 Thunderbolt controller supports D3. */
> > +		if (bridge->is_thunderbolt)
> > +			return true;
> 
> I have a small concern here. In PC world native PCIe hotplug used with
> Thunderbolt comes in two flavors:
> 
>   - Native PCI hotplug without runtime PM
>   - Native PCI hotplug with runtime PM
> 
> The former works so that even if it uses native PCIe hotplug, the power
> management is done so that the Thunderbolt host router is hot-removed
> when there is nothing connected (and that brings the power savings).
> With the above change we start putting all Thunderbolt PCIe hotplug
> ports to D3 runtime. While this probably works (and I tested it on the
> same Dell) I don't think Windows does it and it may lead to a path that
> has not been tested very thoroughly by OEMs.
> 
> So I wonder if it makes sense to restrict this particular check to Apple
> hardware at this point?

I'm not familiar at all with Windows, so this your call.  Normally I'd say,
if there's no known case which forces us to constrain this to Apple, we
probably shouldn't be overzealous.  OTOH I imagine you have to deal with
Windows and broken BIOSes on a daily basis and can anticipate if problems
are to be expected.

The "host router" is the NHI, right?  So IIUC all downstream ports and
the upstream port of the TB PCIe switch may go to D3hot, same for the
root port.  And your concern is that hotplug addition or removal of the
NHI might not work if those ports are in D3hot?

What I don't get is, if we constrain this to Apple, TB ports on non-Apple
systems may not runtime suspend (e.g. if the OEM botched the BIOS date
to be < 2015) and then the "Native PCI hotplug with runtime PM" case
will be broken, won't it?

Thanks,

Lukas

  reply	other threads:[~2018-07-18 20:10 UTC|newest]

Thread overview: 66+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-16 19:25 [PATCH 00/32] Rework pciehp event handling & add runtime PM Lukas Wunner
2018-06-16 19:25 ` [PATCH 15/32] PCI: pciehp: Publish to user space last on probe Lukas Wunner
2018-06-16 19:25 ` [PATCH 09/32] PCI: pciehp: Convert to threaded IRQ Lukas Wunner
2018-06-19 23:16   ` Keith Busch
2018-06-20 11:01     ` Lukas Wunner
2018-06-16 19:25 ` [PATCH 11/32] PCI: pciehp: Stop blinking on slot enable failure Lukas Wunner
2018-06-16 19:25 ` [PATCH 03/32] PCI: pciehp: Fix deadlock on unplug Lukas Wunner
2018-09-06 16:01   ` Mika Westerberg
2018-09-06 16:26     ` Lukas Wunner
2018-09-06 18:08       ` Mika Westerberg
2018-06-16 19:25 ` [PATCH 25/32] PCI: pciehp: Clear spurious events earlier on resume Lukas Wunner
2018-06-16 19:25 ` [PATCH 06/32] PCI: pciehp: Declare pciehp_unconfigure_device() void Lukas Wunner
2018-06-16 19:25 ` [PATCH 31/32] PCI: Whitelist native hotplug ports for runtime D3 Lukas Wunner
2018-06-16 19:25 ` [PATCH 20/32] PCI: pciehp: Tolerate initially unstable link Lukas Wunner
2018-06-16 19:25 ` [PATCH 12/32] PCI: pciehp: Handle events synchronously Lukas Wunner
2018-06-16 19:25 ` [PATCH 27/32] PCI: pciehp: Support interrupts sent from D3hot Lukas Wunner
2018-07-12 23:03   ` Bjorn Helgaas
2018-06-16 19:25 ` [PATCH 18/32] PCI: pciehp: Drop enable/disable lock Lukas Wunner
2018-06-16 19:25 ` [PATCH 17/32] PCI: pciehp: Enable/disable exclusively from IRQ thread Lukas Wunner
2018-06-21 11:58   ` Mika Westerberg
2018-06-16 19:25 ` [PATCH 28/32] PCI: pciehp: Resume to D0 on enable/disable Lukas Wunner
2018-06-16 19:25 ` [PATCH 02/32] PCI: pciehp: Fix UAF on unplug Lukas Wunner
2018-06-16 19:25 ` [PATCH 29/32] PCI: pciehp: Resume parent to D0 on config space access Lukas Wunner
2018-06-16 19:25 ` [PATCH 21/32] PCI: pciehp: Become resilient to missed events Lukas Wunner
2018-06-16 19:25 ` [PATCH 19/32] PCI: pciehp: Declare pciehp_enable/disable_slot() static Lukas Wunner
2018-06-16 19:25 ` [PATCH 05/32] PCI: pciehp: Drop unnecessary NULL pointer check Lukas Wunner
2018-06-16 19:25 ` [PATCH 01/32] PCI: hotplug: Don't leak pci_slot on registration failure Lukas Wunner
2018-06-16 19:25 ` [PATCH 30/32] PCI: sysfs: Resume to D0 on function reset Lukas Wunner
2018-06-16 19:25 ` [PATCH 04/32] PCI: pciehp: Fix unprotected list iteration in IRQ handler Lukas Wunner
2018-06-16 19:25 ` [PATCH 08/32] genirq: Synchronize only with single thread on free_irq() Lukas Wunner
2018-07-12 22:21   ` Bjorn Helgaas
2018-07-13  7:21     ` Lukas Wunner
2018-07-13 11:44       ` Bjorn Helgaas
2018-07-16 12:37       ` Bjorn Helgaas
2018-07-16 13:37         ` Lukas Wunner
2018-06-16 19:25 ` [PATCH 16/32] PCI: pciehp: Track enable/disable status Lukas Wunner
2018-06-16 19:25 ` [PATCH 32/32] PCI: Whitelist Thunderbolt ports for runtime D3 Lukas Wunner
2018-06-21 11:13   ` Mika Westerberg
2018-07-18 19:30     ` Lukas Wunner [this message]
2018-07-20 15:23       ` Mika Westerberg
2018-07-20 16:00         ` Mika Westerberg
2018-07-20 20:33           ` Bjorn Helgaas
2018-06-16 19:25 ` [PATCH 13/32] PCI: pciehp: Drop slot workqueue Lukas Wunner
2018-06-16 19:25 ` [PATCH 14/32] PCI: hotplug: Demidlayer registration with the core Lukas Wunner
2018-06-17 16:44   ` Andy Shevchenko
2018-07-16 12:46     ` Bjorn Helgaas
2018-07-16 14:14       ` Andy Shevchenko
2018-06-16 19:25 ` [PATCH 07/32] PCI: pciehp: Document struct slot and struct controller Lukas Wunner
2018-06-16 19:25 ` [PATCH 10/32] PCI: pciehp: Convert to threaded polling Lukas Wunner
2018-06-16 19:25 ` [PATCH 24/32] PCI: portdrv: Deduplicate PM callback iterator Lukas Wunner
2018-06-16 19:25 ` [PATCH 23/32] PCI: pciehp: Avoid slot access during reset Lukas Wunner
2018-06-21 12:06   ` Mika Westerberg
2018-06-22  9:23     ` Lukas Wunner
2018-06-25 13:10       ` Mika Westerberg
2018-06-16 19:25 ` [PATCH 26/32] PCI: pciehp: Obey compulsory command delay after resume Lukas Wunner
2018-06-16 19:25 ` [PATCH 22/32] PCI: pciehp: Always enable occupied slot on probe Lukas Wunner
2018-06-21 12:19 ` [PATCH 00/32] Rework pciehp event handling & add runtime PM Mika Westerberg
2018-06-27 13:35   ` Patel, Mayurkumar
2018-07-12 22:28 ` Bjorn Helgaas
2018-07-13  7:54   ` Lukas Wunner
2018-07-13 11:43     ` Bjorn Helgaas
2018-07-16 14:20 ` Bjorn Helgaas
2018-07-19  9:43   ` Lukas Wunner
2018-07-19 19:05     ` Bjorn Helgaas
2018-07-19 22:50     ` Bjorn Helgaas
2018-07-28  5:44       ` Lukas Wunner

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20180718193053.GA20124@wunner.de \
    --to=lukas@wunner.de \
    --cc=andreas.noever@gmail.com \
    --cc=ashok.raj@intel.com \
    --cc=bhelgaas@google.com \
    --cc=keith.busch@intel.com \
    --cc=linux-pci@vger.kernel.org \
    --cc=mika.westerberg@linux.intel.com \
    --cc=okaya@kernel.org \
    --cc=rafael.j.wysocki@intel.com \
    --cc=yinghai@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.