From: Imre Deak <imre.deak@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Jani Nikula <jani.nikula@intel.com>,
Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: [PATCH 08/10] drm/i915: Make power well ID names more uniform
Date: Fri, 20 Jul 2018 17:15:02 +0300 [thread overview]
Message-ID: <20180720141504.22832-9-imre.deak@intel.com> (raw)
In-Reply-To: <20180720141504.22832-1-imre.deak@intel.com>
The format for the ID names is <platform>_DISP_PW_* so rename the IDs
not following this accordingly. Leave BXT_DPIO_CMN_BC as-is since we'll
change that to use another existing ID in the next patch.
Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 10 ++++----
drivers/gpu/drm/i915/intel_runtime_pm.c | 44 ++++++++++++++++-----------------
2 files changed, 27 insertions(+), 27 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9b3635009826..b6076f712db5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1036,16 +1036,16 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
enum i915_power_well_id {
DISP_PW_ID_NONE,
- PUNIT_POWER_WELL_DISP2D,
- PUNIT_POWER_WELL_DPIO_CMN_BC,
- PUNIT_POWER_WELL_DPIO_CMN_D,
+ VLV_DISP_PW_DISP2D,
+ BXT_DISP_PW_DPIO_CMN_A,
+ VLV_DISP_PW_DPIO_CMN_BC,
+ GLK_DISP_PW_DPIO_CMN_C,
+ CHV_DISP_PW_DPIO_CMN_D,
HSW_DISP_PW_GLOBAL,
SKL_DISP_PW_MISC_IO,
SKL_DISP_PW_1,
SKL_DISP_PW_2,
- BXT_DPIO_CMN_A,
BXT_DPIO_CMN_BC,
- GLK_DPIO_CMN_C,
ICL_DISP_PW_1,
ICL_DISP_PW_2,
};
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 792394d20f62..56161d0dc3ca 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -768,7 +768,7 @@ static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
{
struct i915_power_well *power_well;
- power_well = lookup_power_well(dev_priv, BXT_DPIO_CMN_A);
+ power_well = lookup_power_well(dev_priv, BXT_DISP_PW_DPIO_CMN_A);
if (power_well->count > 0)
bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy);
@@ -777,7 +777,7 @@ static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy);
if (IS_GEMINILAKE(dev_priv)) {
- power_well = lookup_power_well(dev_priv, GLK_DPIO_CMN_C);
+ power_well = lookup_power_well(dev_priv, GLK_DISP_PW_DPIO_CMN_C);
if (power_well->count > 0)
bxt_ddi_phy_verify_state(dev_priv,
power_well->desc->bxt.phy);
@@ -1129,9 +1129,9 @@ lookup_power_well(struct drm_i915_private *dev_priv,
static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
{
struct i915_power_well *cmn_bc =
- lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
+ lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
struct i915_power_well *cmn_d =
- lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
+ lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
u32 phy_control = dev_priv->chv_phy_control;
u32 phy_status = 0;
u32 phy_status_mask = 0xffffffff;
@@ -1241,10 +1241,10 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
enum pipe pipe;
uint32_t tmp;
- WARN_ON_ONCE(power_well->desc->id != PUNIT_POWER_WELL_DPIO_CMN_BC &&
- power_well->desc->id != PUNIT_POWER_WELL_DPIO_CMN_D);
+ WARN_ON_ONCE(power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC &&
+ power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D);
- if (power_well->desc->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
+ if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
pipe = PIPE_A;
phy = DPIO_PHY0;
} else {
@@ -1272,7 +1272,7 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
- if (power_well->desc->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
+ if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
tmp |= DPIO_DYNPWRDOWNEN_CH1;
vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
@@ -1303,10 +1303,10 @@ static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
{
enum dpio_phy phy;
- WARN_ON_ONCE(power_well->desc->id != PUNIT_POWER_WELL_DPIO_CMN_BC &&
- power_well->desc->id != PUNIT_POWER_WELL_DPIO_CMN_D);
+ WARN_ON_ONCE(power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC &&
+ power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D);
- if (power_well->desc->id == PUNIT_POWER_WELL_DPIO_CMN_BC) {
+ if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
phy = DPIO_PHY0;
assert_pll_disabled(dev_priv, PIPE_A);
assert_pll_disabled(dev_priv, PIPE_B);
@@ -2198,7 +2198,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
.name = "display",
.domains = VLV_DISPLAY_POWER_DOMAINS,
.ops = &vlv_display_power_well_ops,
- .id = PUNIT_POWER_WELL_DISP2D,
+ .id = VLV_DISP_PW_DISP2D,
{
.vlv.idx = PUNIT_PWGT_IDX_DISP2D,
},
@@ -2255,7 +2255,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
.name = "dpio-common",
.domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
.ops = &vlv_dpio_cmn_power_well_ops,
- .id = PUNIT_POWER_WELL_DPIO_CMN_BC,
+ .id = VLV_DISP_PW_DPIO_CMN_BC,
{
.vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
},
@@ -2285,7 +2285,7 @@ static const struct i915_power_well_desc chv_power_wells[] = {
.name = "dpio-common-bc",
.domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
.ops = &chv_dpio_cmn_power_well_ops,
- .id = PUNIT_POWER_WELL_DPIO_CMN_BC,
+ .id = VLV_DISP_PW_DPIO_CMN_BC,
{
.vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
},
@@ -2294,7 +2294,7 @@ static const struct i915_power_well_desc chv_power_wells[] = {
.name = "dpio-common-d",
.domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
.ops = &chv_dpio_cmn_power_well_ops,
- .id = PUNIT_POWER_WELL_DPIO_CMN_D,
+ .id = CHV_DISP_PW_DPIO_CMN_D,
{
.vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D,
},
@@ -2447,7 +2447,7 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
.name = "dpio-common-a",
.domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
.ops = &bxt_dpio_cmn_power_well_ops,
- .id = BXT_DPIO_CMN_A,
+ .id = BXT_DISP_PW_DPIO_CMN_A,
{
.bxt.phy = DPIO_PHY1,
},
@@ -2506,7 +2506,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.name = "dpio-common-a",
.domains = GLK_DPIO_CMN_A_POWER_DOMAINS,
.ops = &bxt_dpio_cmn_power_well_ops,
- .id = BXT_DPIO_CMN_A,
+ .id = BXT_DISP_PW_DPIO_CMN_A,
{
.bxt.phy = DPIO_PHY1,
},
@@ -2524,7 +2524,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.name = "dpio-common-c",
.domains = GLK_DPIO_CMN_C_POWER_DOMAINS,
.ops = &bxt_dpio_cmn_power_well_ops,
- .id = GLK_DPIO_CMN_C,
+ .id = GLK_DISP_PW_DPIO_CMN_C,
{
.bxt.phy = DPIO_PHY2,
},
@@ -3640,9 +3640,9 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
static void chv_phy_control_init(struct drm_i915_private *dev_priv)
{
struct i915_power_well *cmn_bc =
- lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
+ lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
struct i915_power_well *cmn_d =
- lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
+ lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
/*
* DISPLAY_PHY_CONTROL can get corrupted if read. As a
@@ -3727,9 +3727,9 @@ static void chv_phy_control_init(struct drm_i915_private *dev_priv)
static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
{
struct i915_power_well *cmn =
- lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
+ lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
struct i915_power_well *disp2d =
- lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
+ lookup_power_well(dev_priv, VLV_DISP_PW_DISP2D);
/* If the display might be already active skip this */
if (cmn->desc->ops->is_enabled(dev_priv, cmn) &&
--
2.13.2
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next prev parent reply other threads:[~2018-07-20 14:16 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-20 14:14 [PATCH 00/10] drm/i915: Clean up power well descriptors Imre Deak
2018-07-20 14:14 ` [PATCH 01/10] drm/i915/icl: Fix power well anonymous union initializers Imre Deak
2018-07-30 6:07 ` Rodrigo Vivi
2018-08-01 21:01 ` Paulo Zanoni
2018-08-02 23:17 ` Lucas De Marchi
2018-08-03 0:24 ` Paulo Zanoni
2018-08-03 10:23 ` Imre Deak
2018-08-03 21:09 ` Lucas De Marchi
2018-07-20 14:14 ` [PATCH 02/10] drm/i915: Rename intel_power_domains_fini() to intel_power_domains_fini_hw() Imre Deak
2018-07-30 6:09 ` Rodrigo Vivi
2018-08-01 21:02 ` Paulo Zanoni
2018-07-20 14:14 ` [PATCH 03/10] drm/i915/vlv: Remove redundant power well ID asserts Imre Deak
2018-08-01 21:03 ` Paulo Zanoni
2018-07-20 14:14 ` [PATCH 04/10] drm/i915: Constify power well descriptors Imre Deak
2018-08-01 21:39 ` Paulo Zanoni
2018-08-02 12:03 ` Imre Deak
2018-08-02 23:04 ` Paulo Zanoni
2018-07-20 14:14 ` [PATCH 05/10] drm/i915/vlv: Use power well CTL IDX instead of ID Imre Deak
2018-08-01 22:15 ` Paulo Zanoni
2018-08-02 11:56 ` Imre Deak
2018-07-20 14:15 ` [PATCH 06/10] drm/i915/ddi: " Imre Deak
2018-08-02 20:40 ` Paulo Zanoni
2018-08-03 9:13 ` Imre Deak
2018-07-20 14:15 ` [PATCH 07/10] drm/i915: Remove redundant power well IDs Imre Deak
2018-08-02 21:26 ` Paulo Zanoni
2018-08-03 9:31 ` Imre Deak
2018-07-20 14:15 ` Imre Deak [this message]
2018-08-02 21:32 ` [PATCH 08/10] drm/i915: Make power well ID names more uniform Paulo Zanoni
2018-07-20 14:15 ` [PATCH 09/10] drm/i915: Use existing power well IDs where possible Imre Deak
2018-08-02 21:39 ` Paulo Zanoni
2018-08-03 9:34 ` Imre Deak
2018-07-20 14:15 ` [PATCH 10/10] drm/i915/icl: Add missing power gate enums Imre Deak
2018-08-02 21:46 ` Paulo Zanoni
2018-07-20 14:53 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Clean up power well descriptors Patchwork
2018-07-20 14:57 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-07-20 15:15 ` ✓ Fi.CI.BAT: success " Patchwork
2018-07-21 15:39 ` ✓ Fi.CI.IGT: " Patchwork
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